178W9864G6JH-6 Pin descriptionW9864G2IHPublication Release Date: Aug. 28, 2009- 5 - Revision A035. PIN DESCRIPTIONPIN NUMBER PIN NAME FUNCTION DESCRIPTION24, 25, 26, 27, 60, 61, 62,63, 64, 65, 66 A0−A10 AddressMultiplexed pins for row and column address.Row address: A0−A10. Column address: A0−A7.A10 is sampled during a precharge command todetermine if all banks are to be precharged orbank selected by BS0, BS1.22, 23 BS0, BS1 Bank SelectSelect bank to activate during row address latchtime, or bank to read/write during address latchtime.2, 4, 5, 7, 8, 10, 11, 13, 31,33, 34, 36, 37, 39, 40, 42,45, 47, 48, 50, 51, 53, 54,56, 74, 76, 77, 79, 80, 82,83, 85DQ0−DQ31 DataInput/ Output Multiplexed pins for data output and input.20 CS Chip SelectDisable or enable the command decoder. Whencommand decoder is disabled, new command isignored and previous operation continues.19 RAS Row AddressStrobeCommand input. When sampled at the risingedge of the clock RAS , CAS and WEdefine the operation to be executed.18 CAS Column AddressStrobe Referred to RAS17 WE Write Enable Referred to RAS16, 28, 59, 71 DQM0−DQM3 Input/OutputMaskThe output buffer is placed at Hi-Z (with latencyof 2) when DQM is sampled high in read cycle.In write cycle, sampling DQM high will block thewrite operation with zero latency.68 CLK Clock Inputs System clock used to sample inputs on the risingedge of clock.67 CKE Clock EnableCKE controls the clock activation anddeactivation. When CKE is low, Power Downmode, Suspend mode, or Self Refresh mode isentered.1, 15, 29, 43 V DD Power Power for input buffers and logic circuit insideDRAM.44, 58, 72, 86 V SS Ground Ground for input buffers and logic circuit insideDRAM.3, 9, 35, 41, 49, 55, 75, 81 V DDQ Power for I/OBufferSeparated power from VDD, to improve DQnoise immunity.6, 12, 32, 38, 46, 52, 78, 84 V SSQ Ground for I/OBufferSeparated ground from VSS, to improve DQnoise immunity.14, 21, 30, 57, 69, 70, 73 NC No Connection No connection.