Denon AVR-4520CI Service Manual

Contents

225Pin No. Mnemonic Descriptiontrilevel/bilevel input on the SCART or D-terminal connector.AA23 VS_IN2/TRI6 The VS input signal is used for 5-wire timing mode. This ball can also be used as atrilevel/bilevel input on the SCART or D-terminal connector.AB1 GND GroundAB2 TX_PVDD HDMI Tx digital supply (1.8V)AB3 TX_PLVDD HDMI Tx PLL digital supply (1.8V). It is important to ensure that this supply pin has aclean voltage input.AB4 SDVDD Memory interface supplyAB5 A11 SDRAM address lineAB6 A6 SDRAM address lineAB7 A2 SDRAM address lineAB8 CAS SDRAM interface Column Address Select Command Signal. One of four commandsignals to the external SDRAM.AB9 RAS SDRAM interface Row Address Select Command Signal. One of four commandsignals to the external SDRAM.AB10 VREF Termination reference voltage for memory interfaceAB11 SDVDD Memory interface supplyAB12 LDQSN SDRAM lower data strobe compliment signalAB13 DQ3 SDRAM data lineAB14 DQ10 SDRAM data lineAB15 DQ12 SDRAM data lineAB16 DQ14 SDRAM data lineAB17 GND GroundAB18 SYNC1 This is a synchronization on green or luma input (SOG/SOY) used in embeddedsynchronization mode.AB19 AVIN3 Analog video mux input channelAB20 GND GroundAB21 SYNC2 This is a synchronization on green or luma input (SOG/SOY) used in embeddedsynchronization mode.AB22 AVIN6 Analog video mux input channelAB23 TRI4 Digital input capable of slicing bi-level or tri-level input from SCART or D-Connector.AC1 GND GroundAC2 TX_RTERM This signal sets the internal termination resistance. A 500R resistor between this balland GND should be used.AC3 TX_VDD33 HDMI Tx PLL Regulator Supply input (3.3V). This pin is an internal voltage regulatorinput.AC4 SDVDD Memory interface supplyAC5 A8 SDRAM address lineAC6 A4 SDRAM address lineAC7 A0 SDRAM address lineAC8 CS SDRAM interface Chip Select. SDRAM CS Enables and disables the command decoderon the RAM. One of four command signals to the external SDRAM.AC9 CKN SDRAM interface Differential Clock Compliment Output. All address and controloutput signals to the RAM should be sampled on the positive edge of CK and on thenegative edge of CKN.AC10 CK SDRAM interface Differential Clock Right Output. All address and control outputsignals to the RAM should be sampled on the positive edge of CK and on thenegative edge of CKN.AC11 SDVDD Memory interface supplyAC12 LDQS SDRAM lower data strobe true signalAC13 DQ1 SDRAM data lineAC14 DQ9 SDRAM data lineAC15 DQ15 SDRAM data lineAC16 DQ13 SDRAM data lineAC17 GND GroundAC18 AVIN1 Analog video mux input channelAC19 AVIN2 Analog video mux input channelAC20 GND GroundAC21 AVIN4 Analog video mux input channelAC22 AVIN5 Analog video mux input channelAC23 GND Ground