34 IBM System x3850 X6 and x3950 X6 Planning and Implementation GuideFigure 2-25 shows how memory mirroring is implemented in Performance mode (left) andRAS mode (right).Figure 2-25 Memory mirroring with used with Performance mode (left) and RAS mode (right)The following memory mirroring rules apply: The server supports single-socket memory mirroring. The Compute Book memorychannel 0 mirrors memory channel 1, and memory channel 2 mirrors memory channel 3.This mirroring provides redundancy in memory but reduces the total memory capacity inhalf. DIMMs must be installed in pairs for each Compute Book when using the memorymirroring feature. The DIMM population must be identical (size, organization, and so on) for memorychannel 0 and memory channel 1, and identical for memory channel 2 and memorychannel 3. Memory mirroring reduces the maximum available memory by half of the installedmemory. For example, if the server has 64 GB of installed memory, only 32 GB ofaddressable memory is available when memory mirroring is enabled.Rank sparingIn rank-sparing mode, one rank is held in reserve as a spare of the other ranks in the samememory channel. There are eight memory channels per processor.Memory rank sparing provides a degree of redundancy in the memory subsystem, but not tothe extent of mirroring. In contrast to mirroring, sparing leaves more memory for the operatingsystem. In sparing mode, the trigger for failover is a preset threshold of correctable errors.Intel Xeon processorDIMMMemorycontrollerDIMMDIMMMemorycontrollerDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMMemorybufferMemorybufferMemorybufferMemorybufferData’DataIntel Xeon processorDIMMMemorycontrollerDIMMDIMMMemorycontrollerDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMDIMMMemorybufferMemorybufferMemorybufferMemorybufferData’LockstepchannelMemory performance mode+ memory mirroringMemory RAS mode+ memory mirroringMirrorpairsMirrorquadsData
