« FC4A MICRO SMART USER ’S MANUAL » 7-17: B ASIC I NSTRUCTIONSIntroductionThis chapter describes programming of the basic instructions, available operands, and sample programs.All basic instructions are available on all MicroSmart CPU modules.Basic Instruction ListSymbol Name Function Qty ofBytesSeePageAND And Series connection of NO contact 4 7-4AND LOD And Load Series connection of circuit blocks 5 7-5ANDN And Not Series connection of NC contact 4 7-4BPP Bit Pop Restores the result of bit logical operation which wassaved temporarily 2 7-6BPS Bit Push Saves the result of bit logical operation temporarily 5 7-6BRD Bit Read Reads the result of bit logical operation which wassaved temporarily 3 7-6CC= Counter Comparison (=) Equal to comparison of counter current value 7 7-14CC≥ Counter Comparison (≥) Greater than or equal to comparison of counter currentvalue 7 7-14CDP Dual Pulse Reversible Counter Dual pulse reversible counter (0 to 65535) 4 7-10CNT Adding Counter Adding counter (0 to 65535) 4 7-10CUD Up/Down SelectionReversible Counter Up/down selection reversible counter (0 to 65535) 4 7-10DC= Data Register Comparison (=) Equal to comparison of data register value 8 7-16DC≥ Data Register Comparison (≥) Greater than or equal to comparison of data registervalue 8 7-16END End Ends a program 2 7-26JEND Jump End Ends a jump instruction 4 7-25JMP Jump Jumps a designated program area 4 7-25LOD Load Stores intermediate results and reads contact status 6 7-2LODN Load Not Stores intermediate results and reads inverted contactstatus 6 7-2MCR Master Control Reset Ends a master control 4 7-23MCS Master Control Set Starts a master control 4 7-23OR Or Parallel connection of NO contact 4 7-4OR LOD Or Load Parallel connection of circuit blocks 5 7-5ORN Or Not Parallel connection of NC contact 4 7-4OUT Output Outputs the result of bit logical operation 6 7-2OUTN Output Not Outputs the inverted result of bit logical operation 6 7-2RST Reset Resets output, internal relay, or shift register bit 6 7-3SET Set Sets output, internal relay, or shift register bit 6 7-3SFR Shift Register Forward shift register 6 7-18SFRN Shift Register Not Reverse shift register 6 7-18SOTD Single Output Down Falling-edge differentiation output 5 7-22SOTU Single Output Up Rising-edge differentiation output 5 7-22TIM 100-ms Timer Subtracting 100-ms timer (0 to 6553.5 sec) 4 7-7TMH 10-ms Timer Subtracting 10-ms timer (0 to 655.35 sec) 4 7-7TML 1-sec Timer Subtracting 1-sec timer (0 to 65535 sec) 4 7-7TMS 1-ms Timer Subtracting 1-ms timer (0 to 65.535 sec) 4 7-7
