Kenwood NXR-700H Service Manual

NXR-700H152-3. Transmitter modulation 19.2MHz PLL circuitThe transmitter modulation 19.2MHz PLL circuit producesthe reference frequency signal for the Transmitter DDS cir-cuit and modulates the low-frequency components.The circuit consists of IC302, IC303, IC305, X301, Q304,Q305, and Q307.The signal generated by the VCXO (X301) is fed to thebuffer amplifier Q307.The VCXO (X301) signal enters buffer amplifier Q307 andis amplified by Q305. The higher harmonic wave is attenu-ated by the LPF and returns to IC303. Its phase is com-pared with that of the reference frequency 5kHz.The phase difference signal produced by the comparingphase is converted to a DC voltage by a lag-lead type loopfilter. This DC voltage is input to the IC305 invert amplifier(B/2) and is synthesized with the modulating signal. ThisDC voltage is input to the X301 control voltage terminal forcontrolling the VCXO oscillating frequency 19.2MHz.The DC voltage passes through the IC306 operational am-plifier, and is output as a voltage signal (CVT-MOD) for moni-toring the modulating 19.2MHz PLL circuit lock voltage.The 19.2MHz oscillating signal is fed to the Q307 bufferamplifier and is amplified by Q304. The higher harmonicwave is attenuated by the LPF, fed to IC307, and is used asthe reference frequency signal of the transmitter DDS cir-cuit.Q305TX Ref19.2MHzPLL circuit1/R1/NPDFref.=19.2MHzR=3840Fpd=5kHz8V #2Q307X301IC3025V #2IC3055V #2 8V #2 8V #28V #25V #219.2MHzIC306OP-AMPQ3045V #228619.2MHzIC303PLL ICCVT-MODTX DDScircuit19.2MHzMod signalFig. 3 Transmitter modulation 19.2MHz PLL circuit / 图 3 发射机调制 19.2MHz PLL 电路2-4. Transmitter DDS circuitThe transmitter DDS circuit produces the transmittermain PLL reference frequency signal 4.5MHz.This circuit consists of IC307, IC202, CF201, Q210, Q211,Q212 and Q213.The 19.2MHz signal from the transmitter modulation19.2MHz PLL circuit is amplified by IC307 and supplied tothe IC202 reference signal pin.IC202 produces the transmitter main PLL 4.5MHz refer-ence frequency signal based on 19.2MHz on signal.The spurious output by IC202 is attenuated by CF201and LPF, 4.5MHz reference frequency signal is amplifiedby Q211, Q212, and Q213, and fed to the transmitter mainPLL.The comparison frequency of the transmitter main PLL is100kHz and the PLL frequency step is 100kHz.However, minute frequency step such as 2.5kHz and3.125kHz because the DDS output frequency is variable.CIRCUIT DESCRIPTION / 电路说明2-3. 发射机调制 19.2MHz PLL 电路发射机调制 19.2MHz PLL 电路产生发射机 DDS 电路的基准频率信号，并调制低频分量。该电路由 I C302、I C303、I C305、X301、Q304、Q305 和Q307 组成。VCXO(X301) 生成的信号被送入缓冲放大器 Q307。V C X O ( X301) 信号进入缓冲放大器 Q307，由 Q305 放大。较高的谐波由 L P F 衰减并返回 I C303。其相位与基准频率 5k H z的相位进行对比。通过相位对比产生的相位差信号由一个滞后超前式环路滤波器转换为 DC 电压。该 DC 电压被输入 IC305 反相放大器 (B/2)并与调制信号合成。该 D C 电压被输入用于控制 V C X O 振荡频率 19.2MHz 的 X301 控制电压端子。DC 电压通过 IC306 运算放大器，输出为电压信号 (CVT-MOD)，用于监测调制 19.2MHz PLL 电路锁定电压。19.2M H z 振荡信号被送入 Q307 缓冲放大器，由 Q304 放大。较高的谐波由 LPF 衰减，送入 IC307，用作发射机 DDS 电路的基准频率信号。2-4. 发射机 DDS 电路发射机 DDS 电路产生发射机主 PLL 基准频率信号 4.5MHz。该电路由 I C307、I C202、C F201、Q210、Q211、Q212 和Q213 组成。来自发射机调制 19.2M H z P L L 电路的 19.2M H z 信号由IC307 放大并提供给 IC202 基准信号针脚。IC202 产生基于信号上的 19.2MHz 的 PLL 4.5MHz 基准频率信号。I C202 的寄生输出由 C F201 和 L P F 衰减，4.5M H z 基准频率信号由 Q211、Q212 和 Q213 放大，并被送入发射机主 PLL。发射机主 P L L 的比较频率为 100k H z，P L L 频率步长为100kHz。但是，微小频率步长为 2.5k H z 和 3.125k H z，因为 D D S 输出频率是可变的。