NXR-700H25D15SWD16SWCF2CF3D19SWD20SWDETCF5CF7QUAD108641517 IC20(A/2)Q40IC29 (A/2)D17,18IC3011 181218212414 8 10DIV2nd local49.5MHz2nd local49.5MHz6CF4CF6145DR3DR5NRAnalog WideAnalog NarrowNXDN NarrowNXDN Very-NarrowIC12IC13IC14CN421222CN43Fig. 19 Demodulator circuits / 图 19 解调器电路4-6. Receiver DDS circuitThe 19.2MHz Internal reference clock produced by trans-mitter unit (X56-311 A/3) is distributed to CN45 of the re-ceiver unit (X55-309). It passes through Q39, Q30, and IC8,and is input to IC7 (DDS-IC) pin6 as the Master clock. Ap-proximately 6MHz signal is generated as the 1st-PLL Refer-ence clock.IC7 has a resolution of 32 bits for realizing the frequencystep minters than the 1st-PLL comparison frequency. Thegenerated Reference clock is output via Q12, CF1, and Q5.CF1 is a Ceramic Filter. It is the BPF for removing unneces-sary spurious noise included in the generated Referenceclock.LPF LPF LPF LPFBPF+5VQ5+5V +5VQ12+5VQ30+5VQ39CF1IC7DDS14 6+5VIC81 5DIV CN45Fig. 20 Receiver DDS circuit / 图 20 接收机 DDS 电路CIRCUIT DESCRIPTION / 电路说明4-6. 接收机 DDS 电路发射机单元 ( X56-311 A /3) 产生的 19.2M H z 内部基准时钟被分配到接收机单元 (X55-309) 的 CN45。它通过 Q39、Q30 和IC8,被输入到 IC7(DDS-IC) 针脚 6 作为主时钟。生成约 6MHz信号,作为第 1 PLL 基准时钟。I C7 具有 32 位的分辨率,用于实现小于第 1 P L L 比较频率的频率步长。生成的基准时钟经 Q12、CF1 和 Q5 输出。CF1 是一个陶瓷滤波器。它是消除所生成基准时钟中包含的不需要的寄生噪声的 BPF。