Contents - Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- Table Of Contents
- CHAPTER 1 INTRODUCTION
- Application Fields
- Pin Configuration (Top View)
- Function Blocks
- On-chip units
- CHAPTER 2 PIN FUNCTIONS
- Pin States
- Description of Pin Functions
- Pins' I/O Circuit Types and Handling When Not Used
- Pins' I/O Circuits
- CHAPTER 3 CPU FUNCTIONS
- CPU Register Set
- Program register set
- System register set
- Operation Modes
- Address Space
- Image (virtual address space)
- Wrap-around of CPU address space
- Memory map
- Area
- Interrupt/Exception Table
- External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)
- External Memory Area (when expanded to 4 Mbytes)
- External expansion mode
- Memory Expansion Mode Register (MM) Format
- Memory Address Output Mode Register (MAM) Format
- Recommended use of address space
- Recommended Memory Map (Flash Memory Internal Version)
- Peripheral I/O registers
- Specific registers
- CHAPTER 4 BUS CONTROL FUNCTION
- Control register
- Bus width
- Memory Block Function
- Wait Function
- External wait function
- Idle State Insertion Function
- Bus Hold Function
- Bus hold procedure
- Bus Timing
- Bus Priority
- Features
- Interrupt Source List
- Non-Maskable Interrupt
- Accepting operation
- Accepting Non-Maskable Interrupt Request
- Restore
- NP flag
- Edge detection function of NMI pin
- Maskable Interrupts
- Maskable Interrupt Processing
- Priorities of maskable interrupts
- Example of Interrupt Nesting Process
- Example of Processing Interrupt Requests Simultaneously Generated
- Interrupt control register (xxICn)
- In-service priority register (ISPR)
- Watchdog timer mode register (WDTM)
- Edge detection function
- Software Exception
- EP flag
- RETI Instruction Processing
- Priority Control
- Interrupt Latency Time
- CHAPTER 6 CLOCK GENERATION FUNCTION
- Clock Output Function
- Format of Power Saving Control Register (PSC)
- Power Saving Functions
- HALT mode
- Operating Statuses during HALT Mode
- IDLE mode
- Software STOP mode
- Oscillation Stabilization Time
- CHAPTER 7 TIMER/COUNTER FUNCTION
- Block Diagram of TM0 and TM1
- Configuration
- Valid Edge of TIn0 Pin and Capture Trigger of CRn0
- Timer 0, 1 Control Register
- Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1)
- Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)
- Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)
- Format of Prescaler Mode Register 0 (PRM0)
- Format of Prescaler Mode Register 1 (PRM1)
- Operation
- Configuration of Interval Timer
- PPG output operation
- Pulse width measurement
- Configuration for Pulse Width Measurement with Free Running Counter
- Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter
- CRn1 Capture Operation with Rising Edge Specified
- Control Register Settings for Pulse Width Measurement by Restarting
- Operation as external event counter
- Operation to output square wave
- Control Register Settings in Square Wave Output Mode
- Operation to output one-shot pulse
- Control Register Settings for One-Shot Pulse Output with Software Trigger
- Timing of One-Shot Pulse Output Operation with Software Trigger
- Control Register Settings for One-Shot Pulse Output with External Trigger
- Cautions
- Timing after Changing Compare Register during Timer Count Operation
- Operation Timing of OVFn Flag
- bit Timer (TM2-TM5)
- Timer n control register
- Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)
- Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5)
- Operating as external event counter
- Operating as square wave output (8-bit resolution)
- Operating as 8-bit PWM output
- Timing of PWM Output
- Timing of Operation Based on CRn0 Transitions
- Cascade Connection Mode with 16-Bit Resolution
- CHAPTER 8 WATCH TIMER
- Watch Timer Control Register
- Operation as interval timer
- CHAPTER 9 WATCHDOG TIMER
- Runaway Detection Time for Watchdog Timer
- Format of Watchdog Timer Clock Selection Register (WDCS)
- Format of Watchdog Timer Mode Register (WDTM)
- Operating as interval timer
- Standby Function Control Register
- CHAPTER 10 SERIAL INTERFACE FUNCTION
- CSIn control registers
- Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)
- Operations
- Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)
- Timing of 3-wire Serial I/O Mode
- Format of IIC Control Register (IICC0)
- Format of IIC Status Register (IICS0)
- Format of IIC Clock Select Register (IICCL0)
- Pin Configuration Diagram
- Start Conditions
- Address
- Transfer Direction Specification
- ACK Signal
- Stop Condition
- Wait Signal
- Interrupt request (INTIIC0) generation timing and wait control
- Address match detection method
- Error detection
- Arbitration
- Arbitration Timing Example
- Wake up function
- Communication reservation
- Communication Reservation Timing
- Timing for Accepting Communication Reservations
- Communication Reservation Flow Chart
- Other cautions
- Communication operations
- Slave Operation Flow Chart
- Timing of data communication
- Asynchronous Serial Interface (UART0, UART1)
- Block Diagram of UARTn
- UARTn control registers
- Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1)
- Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)
- Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)
- Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)
- Asynchronous serial interface (UARTn) mode
- Relation between Main Clock and Baud Rate
- Error Tolerance (when k = 0), including Sampling Errors
- Format of Transmit/Receive Data in Asynchronous Serial Interface
- Timing of Asynchronous Serial Interface Transmit Completion Interrupt
- Timing of Asynchronous Serial Interface Receive Completion Interrupt
- Receive Error Timing
- Standby function
- CHAPTER 11 A/D CONVERTER
- Block Diagram of A/D Converter
- Control Registers
- Format of Analog Input Channel Specification Register (ADS)
- Basic Operation of A/D Converter
- Input voltage and conversion result
- A/D converter operation mode
- A/D Conversion by Hardware Start (with falling edge specified)
- A/D Conversion by Software Start
- Notes on Using A/D Converter
- Processing of Analog Input Pin
- A/D Conversion End Interrupt Generation Timing
- CHAPTER 12 DMA FUNCTIONS
- Format of DMA On-chip RAM Address Registers 0 to 2 (DRA0 to DRA2)
- Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2)
- CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO)
- RTO Control Registers
- Format of Real-Time Output Port Mode Register (RTPM)
- Format of Real-Time Output Port Control Register (RTPC)
- Usage
- CHAPTER 14 PORT FUNCTION
- Format of Port 0 Mode Register (PM0)
- Format of Rising Edge Enable Register (EGP0)
- Port 1
- Format of Port 1 Mode Register (PM1)
- Format of Pull-up Resistance Option Register 1 (PU1)
- Port 2
- Format of Port 2 Mode Register (PM2)
- Format of Pull-up Resistance Option Register 2 (PU2)
- Port 3
- Format of Port 3 Mode Register (PM3)
- Ports 4 and 5
- Port 6
- Format of Port 6 Mode Register (PM6)
- Ports 7 and 8
- Port 9
- Format of Port 9 Mode Register (PM9)
- Port 10
- Format of Port 10 Mode Register (PM10)
- Port 11
- Format of Port 11 (P11)
- Format of Port 11 Mode Register (PM11)
- Port 12
- Format of Port 12 Mode Register (PM12)
- Format of Port 12 Mode Control Register (PMC12)
- CHAPTER 15 RESET FUNCTION
- CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017, 70F3017Y)
- Programming Environment
- Pin Connection
- RESET pin
- Programming Method
- Selection of communication mode
- Resources used
- APPENDIX A REGISTER INDEX
- APPENDIX B LIST OF INSTRUTION SET
- APPENDIX C INDEX
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104.3.2 Bus width..................................................................................................................................... 854.4 Memory Block Function....................................................................................................................... 864.5 Wait Function........................................................................................................................................ 874.5.1 Programmable wait function ........................................................................................................ 874.5.2 External wait function .................................................................................................................. 884.5.3 Relations between programmable wait and external wait ........................................................... 884.6 Idle State Insertion Function ............................................................................................................... 894.7 Bus Hold Function................................................................................................................................ 904.7.1 Outline of function ....................................................................................................................... 904.7.2 Bus hold procedure ..................................................................................................................... 914.7.3 Operation in power save mode ................................................................................................... 914.8 Bus Timing............................................................................................................................................ 924.9 Bus Priority ........................................................................................................................................... 994.10 Memory Boundary Operation Condition ............................................................................................ 994.10.1 Program space .......................................................................................................................... 994.10.2 Data space ................................................................................................................................ 99CHAPTER 5 INTERRUPT/EXCEPTION PROCESSING FUNCTION................................................. 1015.1 Features ................................................................................................................................................ 1015.2 Non-Maskable Interrupt ....................................................................................................................... 1045.2.1 Accepting operation..................................................................................................................... 1055.2.2 Restore........................................................................................................................................ 1075.2.3 NP flag......................................................................................................................................... 1085.2.4 Noise elimination circuit of NMI pin ............................................................................................. 1085.2.5 Edge detection function of NMI pin ............................................................................................. 1095.3 Maskable Interrupts.............................................................................................................................. 1105.3.1 Operation..................................................................................................................................... 1105.3.2 Restore........................................................................................................................................ 1125.3.3 Priorities of maskable interrupts .................................................................................................. 1135.3.4 Interrupt control register (xxICn).................................................................................................. 1175.3.5 In-service priority register (ISPR) ................................................................................................ 1195.3.6 Maskable interrupt status flag ..................................................................................................... 1195.3.7 Watchdog timer mode register (WDTM)...................................................................................... 1205.3.8 Noise elimination ......................................................................................................................... 1205.3.9 Edge detection function............................................................................................................... 1215.4 Software Exception .............................................................................................................................. 1225.4.1 Operation..................................................................................................................................... 1225.4.2 Restore........................................................................................................................................ 1235.4.3 EP flag......................................................................................................................................... 1245.5 Exception Trap ..................................................................................................................................... 1245.5.1 Illegal op code definition.............................................................................................................. 1245.5.2 Operation..................................................................................................................................... 1245.5.3 Restore........................................................................................................................................ 1255.6 Priority Control ..................................................................................................................................... 1275.6.1 Priorities of interrupts and exceptions ......................................................................................... 1275.6.2 Multiple interrupt processing ....................................................................................................... 1275.7 Interrupt Latency Time......................................................................................................................... 130
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