317CHAPTER 12 DMA FUNCTIONS12.1 FunctionsThe DMA (Direct Memory Access) controller transfers data between memory and peripheral I/Os based on DMArequests sent from on-chip peripheral hardware (such as the serial interface, timer, or A/D converter).This product includes three independent DMA channels that can transfer data in 8-bit and 16-bit units. Themaximum number of transfers is 256 and transfers are enabled only in single transfer mode.After a DMA transfer is completed, DMA transfer completion interrupt (INTDMA0 to INTDMA2) requests are outputindependently from the various channels.The priority levels of the DMA channels are fixed as follows.DMA0 > DMA1 > DMA212.2 Transfer Completion Interrupt RequestWhen a DMA transfer is completed and the TCn bit in the corresponding DMA channel control register (DCHCn) hasbeen set (to “1”), a DMA transfer completion interrupt request (INTDMA0 to INTDMA2) occurs on each channel inrelation to the interrupt controller.12.3 Control Registers(1) DMA peripheral I/O address registers 0 to 2 (DIOA0 to DIOA2)These registers are used to set the peripheral I/O register’s address for DMA channel n. There is noincrementation function.Read and write in 16-bit units are enabled.Figure 12-1. Format of DMA Peripheral I/O Address Registers 0 to 2 (DIOA0 to DIOA2)After reset: undefined R/W Address : DIOA0 FFFFF180HDIOA1 FFFFF190HDIOA2 FFFFF1A0H15 14 13 12 11 10 9 1 0DIOAn 0 0 0 0 0 0 IOAn9-IOAn1 0(n = 0-2)Caution The following peripheral I/O registers cannot be set.P4, P5, P6, P9, P11, P12, PM4, PM5, PM6, PM9, PM11, PM12, PMC12, MM, DWC, BCC, SYC,PSC, PCC, SYS, PRCMD, DIOAn, DRAn, DBCn, DCHCn
