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NEC V850/SA1 mPD703015 Preliminary User's Manual

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Contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. CHAPTER 1 INTRODUCTION
  14. Application Fields
  15. Pin Configuration (Top View)
  16. Function Blocks
  17. On-chip units
  18. CHAPTER 2 PIN FUNCTIONS
  19. Pin States
  20. Description of Pin Functions
  21. Pins' I/O Circuit Types and Handling When Not Used
  22. Pins' I/O Circuits
  23. CHAPTER 3 CPU FUNCTIONS
  24. CPU Register Set
  25. Program register set
  26. System register set
  27. Operation Modes
  28. Address Space
  29. Image (virtual address space)
  30. Wrap-around of CPU address space
  31. Memory map
  32. Area
  33. Interrupt/Exception Table
  34. External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)
  35. External Memory Area (when expanded to 4 Mbytes)
  36. External expansion mode
  37. Memory Expansion Mode Register (MM) Format
  38. Memory Address Output Mode Register (MAM) Format
  39. Recommended use of address space
  40. Recommended Memory Map (Flash Memory Internal Version)
  41. Peripheral I/O registers
  42. Specific registers
  43. CHAPTER 4 BUS CONTROL FUNCTION
  44. Control register
  45. Bus width
  46. Memory Block Function
  47. Wait Function
  48. External wait function
  49. Idle State Insertion Function
  50. Bus Hold Function
  51. Bus hold procedure
  52. Bus Timing
  53. Bus Priority
  54. Features
  55. Interrupt Source List
  56. Non-Maskable Interrupt
  57. Accepting operation
  58. Accepting Non-Maskable Interrupt Request
  59. Restore
  60. NP flag
  61. Edge detection function of NMI pin
  62. Maskable Interrupts
  63. Maskable Interrupt Processing
  64. Priorities of maskable interrupts
  65. Example of Interrupt Nesting Process
  66. Example of Processing Interrupt Requests Simultaneously Generated
  67. Interrupt control register (xxICn)
  68. In-service priority register (ISPR)
  69. Watchdog timer mode register (WDTM)
  70. Edge detection function
  71. Software Exception
  72. EP flag
  73. RETI Instruction Processing
  74. Priority Control
  75. Interrupt Latency Time
  76. CHAPTER 6 CLOCK GENERATION FUNCTION
  77. Clock Output Function
  78. Format of Power Saving Control Register (PSC)
  79. Power Saving Functions
  80. HALT mode
  81. Operating Statuses during HALT Mode
  82. IDLE mode
  83. Software STOP mode
  84. Oscillation Stabilization Time
  85. CHAPTER 7 TIMER/COUNTER FUNCTION
  86. Block Diagram of TM0 and TM1
  87. Configuration
  88. Valid Edge of TIn0 Pin and Capture Trigger of CRn0
  89. Timer 0, 1 Control Register
  90. Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1)
  91. Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)
  92. Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)
  93. Format of Prescaler Mode Register 0 (PRM0)
  94. Format of Prescaler Mode Register 1 (PRM1)
  95. Operation
  96. Configuration of Interval Timer
  97. PPG output operation
  98. Pulse width measurement
  99. Configuration for Pulse Width Measurement with Free Running Counter
  100. Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter
  101. CRn1 Capture Operation with Rising Edge Specified
  102. Control Register Settings for Pulse Width Measurement by Restarting
  103. Operation as external event counter
  104. Operation to output square wave
  105. Control Register Settings in Square Wave Output Mode
  106. Operation to output one-shot pulse
  107. Control Register Settings for One-Shot Pulse Output with Software Trigger
  108. Timing of One-Shot Pulse Output Operation with Software Trigger
  109. Control Register Settings for One-Shot Pulse Output with External Trigger
  110. Cautions
  111. Timing after Changing Compare Register during Timer Count Operation
  112. Operation Timing of OVFn Flag
  113. bit Timer (TM2-TM5)
  114. Timer n control register
  115. Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)
  116. Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5)
  117. Operating as external event counter
  118. Operating as square wave output (8-bit resolution)
  119. Operating as 8-bit PWM output
  120. Timing of PWM Output
  121. Timing of Operation Based on CRn0 Transitions
  122. Cascade Connection Mode with 16-Bit Resolution
  123. CHAPTER 8 WATCH TIMER
  124. Watch Timer Control Register
  125. Operation as interval timer
  126. CHAPTER 9 WATCHDOG TIMER
  127. Runaway Detection Time for Watchdog Timer
  128. Format of Watchdog Timer Clock Selection Register (WDCS)
  129. Format of Watchdog Timer Mode Register (WDTM)
  130. Operating as interval timer
  131. Standby Function Control Register
  132. CHAPTER 10 SERIAL INTERFACE FUNCTION
  133. CSIn control registers
  134. Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)
  135. Operations
  136. Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)
  137. Timing of 3-wire Serial I/O Mode
  138. Format of IIC Control Register (IICC0)
  139. Format of IIC Status Register (IICS0)
  140. Format of IIC Clock Select Register (IICCL0)
  141. Pin Configuration Diagram
  142. Start Conditions
  143. Address
  144. Transfer Direction Specification
  145. ACK Signal
  146. Stop Condition
  147. Wait Signal
  148. Interrupt request (INTIIC0) generation timing and wait control
  149. Address match detection method
  150. Error detection
  151. Arbitration
  152. Arbitration Timing Example
  153. Wake up function
  154. Communication reservation
  155. Communication Reservation Timing
  156. Timing for Accepting Communication Reservations
  157. Communication Reservation Flow Chart
  158. Other cautions
  159. Communication operations
  160. Slave Operation Flow Chart
  161. Timing of data communication
  162. Asynchronous Serial Interface (UART0, UART1)
  163. Block Diagram of UARTn
  164. UARTn control registers
  165. Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1)
  166. Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)
  167. Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)
  168. Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)
  169. Asynchronous serial interface (UARTn) mode
  170. Relation between Main Clock and Baud Rate
  171. Error Tolerance (when k = 0), including Sampling Errors
  172. Format of Transmit/Receive Data in Asynchronous Serial Interface
  173. Timing of Asynchronous Serial Interface Transmit Completion Interrupt
  174. Timing of Asynchronous Serial Interface Receive Completion Interrupt
  175. Receive Error Timing
  176. Standby function
  177. CHAPTER 11 A/D CONVERTER
  178. Block Diagram of A/D Converter
  179. Control Registers
  180. Format of Analog Input Channel Specification Register (ADS)
  181. Basic Operation of A/D Converter
  182. Input voltage and conversion result
  183. A/D converter operation mode
  184. A/D Conversion by Hardware Start (with falling edge specified)
  185. A/D Conversion by Software Start
  186. Notes on Using A/D Converter
  187. Processing of Analog Input Pin
  188. A/D Conversion End Interrupt Generation Timing
  189. CHAPTER 12 DMA FUNCTIONS
  190. Format of DMA On-chip RAM Address Registers 0 to 2 (DRA0 to DRA2)
  191. Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2)
  192. CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO)
  193. RTO Control Registers
  194. Format of Real-Time Output Port Mode Register (RTPM)
  195. Format of Real-Time Output Port Control Register (RTPC)
  196. Usage
  197. CHAPTER 14 PORT FUNCTION
  198. Format of Port 0 Mode Register (PM0)
  199. Format of Rising Edge Enable Register (EGP0)
  200. Port 1
  201. Format of Port 1 Mode Register (PM1)
  202. Format of Pull-up Resistance Option Register 1 (PU1)
  203. Port 2
  204. Format of Port 2 Mode Register (PM2)
  205. Format of Pull-up Resistance Option Register 2 (PU2)
  206. Port 3
  207. Format of Port 3 Mode Register (PM3)
  208. Ports 4 and 5
  209. Port 6
  210. Format of Port 6 Mode Register (PM6)
  211. Ports 7 and 8
  212. Port 9
  213. Format of Port 9 Mode Register (PM9)
  214. Port 10
  215. Format of Port 10 Mode Register (PM10)
  216. Port 11
  217. Format of Port 11 (P11)
  218. Format of Port 11 Mode Register (PM11)
  219. Port 12
  220. Format of Port 12 Mode Register (PM12)
  221. Format of Port 12 Mode Control Register (PMC12)
  222. CHAPTER 15 RESET FUNCTION
  223. CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017, 70F3017Y)
  224. Programming Environment
  225. Pin Connection
  226. RESET pin
  227. Programming Method
  228. Selection of communication mode
  229. Resources used
  230. APPENDIX A REGISTER INDEX
  231. APPENDIX B LIST OF INSTRUTION SET
  232. APPENDIX C INDEX
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This manual is suitable for:
V850/SA1 mPD703015V850/SA1 mPD703015YV850/SA1 mPD70F3017V850/SA1 mPD70F3017Y
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