CHAPTER 4 BUS CONTROL FUNCTION994.9 Bus PriorityThere are four external bus cycles: bus hold, operand data access, instruction fetch (branch), and instruction fetch(continuous). The bus hold cycle is given the highest priority, followed by operand data access, instruction fetch(branch), and instruction fetch (continuous) in that order.The instruction fetch cycle may be inserted in between the read access and write access of read-modify-write ac-cess.No instruction fetch cycle and bus hold are inserted between the lower half-word access and higher half-word ac-cess of word operations.Table 4-1. Bus PriorityExternal Bus Cycle PriorityBus hold 1Operand data access 2Instruction fetch (branch) 3Instruction fetch (continuous) 44.10 Memory Boundary Operation Condition4.10.1 Program space(1) Do not execute branch to the on-chip peripheral I/O area or continuous fetch from the internal RAM area to pe-ripheral I/O area. Of course, it is impossible to fetch from external memory. If branch or instruction fetch is exe-cuted nevertheless, the NOP instruction code is continuously fetched.(2) A prefetch operation straddling over the on-chip peripheral I/O area (invalid fetch) does not take place if a branchinstruction exists at the upper-limit address of the internal RAM area.4.10.2 Data spaceOnly the address aligned at the half-word (when the least significant bit of the address is “0”)/word (when the low-est 2 bits of the address are “0”) boundary is accessed for data half-word (16 bits)/word (32 bits) long.Therefore, access that straddles over the memory or memory block boundary does not take place.For the details, refer to V850 Family User’s Manual Architecture.
