CHAPTER 5 CLOCK GENERATOR104 User’s Manual U11302EJ4V0UMThe fastest instruction of theμPD780208 Subseries is executed in two CPU clocks. Therefore, the relationshipbetween the CPU clock (f CPU ) and minimum instruction execution time is as shown in Table 5-2.Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution TimeCPU Clock (f CPU ) Minimum Instruction Execution Time: 2/f CPUf X 0.4μsf X /2 0.8μsf X /2 2 1.6μsf X /2 3 3.2μsf X /2 4 6.4μsf XT /2 122μsf X = 5.0 MHz, f XT = 32.768 kHzf X : Main system clock oscillation frequencyf XT : Subsystem clock oscillation frequency(2) Display mode register 0 (DSPM0)This register sets the mode for the noise eliminator of the subsystem clock.DSPM0 is set with an 8-bit memory manipulation instruction.Only bit 7 (KSF) can be read with a 1-bit memory manipulation instruction.RESET input sets DSPM0 to 00H.Remark In addition to the function mentioned above, DSPM0 can also set the number of display segments/total number of display outputs, display mode, and display key scan timing.
