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NEC mPD780208 Subseries User Manual

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Contents
  1. User's Manual U11302EJ4V0UM
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. Table Of Contents
  14. Table Of Contents
  15. Table Of Contents
  16. CHAPTER 1 OUTLINE
  17. Applications
  18. Pin Configuration (Top View)
  19. K/0 Series Lineup
  20. Block Diagram
  21. Overview of Functions
  22. Mask Options
  23. CHAPTER 2 PIN FUNCTIONS
  24. Description of Pin Functions
  25. P20 to P27 (Port
  26. P70 to P74 (Port
  27. 2.2.11 FIP0 to FIP12
  28. 2.2.12 V LOAD
  29. Pin I/O Circuits and Recommended Connection of Unused Pins
  30. Pin I/O Circuits
  31. CHAPTER 3 CPU ARCHITECTURE
  32. Memory Map ( µ PD780205 and µ PD780205A)
  33. Memory Map ( µ PD780206)
  34. Memory Map ( µ PD780208)
  35. Memory Map ( µ PD78P0208)
  36. Internal ROM Capacity
  37. Data memory addressing
  38. Data Memory Addressing ( µ PD780205 and µ PD780205A)
  39. Data Memory Addressing ( µ PD780206)
  40. Data Memory Addressing ( µ PD780208)
  41. Data Memory Addressing ( µ PD78P0208)
  42. Processor Registers
  43. Stack Pointer Format
  44. Data to Be Saved to Stack Memory
  45. General-purpose registers
  46. Special-function registers (SFRs)
  47. Special-Function Register List
  48. Instruction Address Addressing
  49. Immediate addressing
  50. Table indirect addressing
  51. Register addressing
  52. Operand Address Addressing
  53. Direct addressing
  54. Short direct addressing
  55. Special-function register (SFR) addressing
  56. Register indirect addressing
  57. Based addressing
  58. Based indexed addressing
  59. Port Functions
  60. Port Configuration
  61. Block Diagram of P00 and P04
  62. Port 1
  63. Port 2
  64. Block Diagram of P22 and P27
  65. Port 3
  66. Port 7
  67. Port 8
  68. Port 9
  69. Port 10
  70. Port 11
  71. Port 12
  72. Port Function Control Registers
  73. Format of Port Mode Register
  74. Format of Pull-up Resistor Option Register
  75. Port Function Operations
  76. Selection of Mask Option
  77. Clock Generator Functions
  78. Clock Generator Control Registers
  79. Format of Processor Clock Control Register
  80. Relationship Between CPU Clock and Minimum Instruction Execution Time
  81. Format of Display Mode Register 0
  82. Format of Display Mode Register 1
  83. System Clock Oscillator
  84. Subsystem clock oscillator
  85. Examples of Incorrect Resonator Connection
  86. Divider
  87. Clock Generator Operations
  88. Main system clock operations
  89. Subsystem clock operations
  90. Changing System Clock and CPU Clock Settings
  91. System clock and CPU clock switching procedure
  92. CHAPTER 6 16-BIT TIMER/EVENT COUNTER
  93. Bit Timer/Event Counter Functions
  94. Bit Timer/Event Counter Interval Time
  95. Bit Timer/Event Counter Configuration
  96. Bit Timer/Event Counter Control Registers
  97. Format of Timer Clock Select Register 0
  98. Format of 16-Bit Timer Mode Control Register
  99. Format of 16-Bit Timer Output Control Register
  100. Format of Port Mode Register 3
  101. Format of External Interrupt Mode Register
  102. Format of Sampling Clock Select Register
  103. Bit Timer/Event Counter Operations
  104. Interval Timer Operation Timing
  105. PWM output operations
  106. Pulse width measurement operations
  107. Configuration Diagram for Pulse Width Measurement in Free-Running Mode
  108. External event counter operation
  109. External Event Counter Configuration Diagram
  110. Square-wave output operation
  111. Bit Timer/Event Counter Operating Precautions
  112. Capture Register Data Retention Timing
  113. CHAPTER 7 8-BIT TIMER/EVENT COUNTER
  114. Bit Timer/Event Counter Square-Wave Output Ranges
  115. bit timer/event counter mode
  116. Block Diagram of 8-Bit Timer/Event Counter Output Controller 1
  117. Format of Timer Clock Select Register 1
  118. Format of 8-Bit Timer Mode Control Register
  119. Format of 8-Bit Timer Output Control Register
  120. Bit Timer/Event Counter 1 Interval Time
  121. External Event Counter Operation Timing (with Rising Edge Specified)
  122. Square-Wave Output Operation Timing
  123. Timing After Compare Register Change During Timer Count Operation
  124. CHAPTER 8 WATCH TIMER
  125. Watch Timer Configuration
  126. Format of Timer Clock Select Register 2
  127. Format of Watch Timer Mode Control Register
  128. Watch Timer Operations
  129. CHAPTER 9 WATCHDOG TIMER
  130. Watchdog Timer Configuration
  131. Watchdog Timer Control Registers
  132. Format of Watchdog Timer Mode Register
  133. Watchdog Timer Operations
  134. Interval timer operation
  135. CHAPTER 10 CLOCK OUTPUT CONTROLLER
  136. Clock Output Controller Configuration
  137. CHAPTER 11 BUZZER OUTPUT CONTROLLER
  138. Buzzer Output Function Control Registers
  139. CHAPTER 12 A/D CONVERTER
  140. A/D Converter Block Diagram
  141. A/D Converter Control Registers
  142. Format of A/D Converter Mode Register
  143. Format of A/D Converter Input Select Register
  144. A/D Converter Operations
  145. Basic Operation of A/D Converter
  146. Input voltage and conversion results
  147. A/D converter operating mode
  148. A/D Conversion by Software Start
  149. A/D Converter Precautions
  150. Analog Input Pin Processing
  151. A/D Conversion End Interrupt Request Generation Timing
  152. CHAPTER 13 SERIAL INTERFACE CHANNEL 0
  153. Functions of Serial Interface Channel 0
  154. Configuration of Serial Interface Channel 0
  155. Control Registers of Serial Interface Channel 0
  156. Format of Timer Clock Select Register 3
  157. Format of Serial Operating Mode Register 0
  158. Format of Serial Bus Interface Control Register
  159. Format of Interrupt Timing Specification Register
  160. Operations of Serial Interface Channel 0
  161. wire serial I/O mode operation
  162. Wire Serial I/O Mode Timing
  163. RELT and CMDT Operations
  164. SBI mode operation
  165. Example of Serial Bus Configuration with SBI
  166. SBI Transfer Timing
  167. Bus Release Signal
  168. Address
  169. Commands
  170. Acknowledge Signal
  171. BUSY and READY Signals
  172. RELT, CMDT, RELD, and CMDD Operations (Master)
  173. ACKT Operation
  174. ACKE Operations
  175. ACKD Operations
  176. Pin Configuration
  177. SCK0/P27 pin output manipulation
  178. CHAPTER 14 SERIAL INTERFACE CHANNEL 1
  179. Configuration of Serial Interface Channel 1
  180. Control Registers of Serial Interface Channel 1
  181. Format of Serial Operating Mode Register 1
  182. Format of Automatic Data Transmit/Receive Control Register
  183. Format of Automatic Data Transmit/Receive Interval Specification Register
  184. Operations of Serial Interface Channel 1
  185. Circuit for Switching Transfer Bit Order
  186. wire serial I/O mode operation with automatic transmit/receive function
  187. Basic Transmission/Reception Mode Operation Timing
  188. Basic Transmission/Reception Mode Flowchart
  189. Basic Transmission Mode Operation Timing
  190. Basic Transmission Mode Flowchart
  191. Buffer RAM Operation in 6-Byte Transmission (in Basic Transmission Mode)
  192. Repeat Transmission Mode Operation Timing
  193. Repeat Transmission Mode Flowchart
  194. Buffer RAM Operation in 6-Byte Transmission (in Repeat Transmission Mode)
  195. Automatic Transmission/Reception Suspension and Restart
  196. System Configuration with Busy Control Option
  197. Operation Timing When Using Busy Control Option (BUSY0 = 0)
  198. Operation Timing When Using Busy & Strobe Control Option (BUSY0 = 0)
  199. Operation Timing of Bit Slippage Detection Function Using Busy Signal (BUSY0 = 1)
  200. Automatic Transmit/Receive Interval
  201. Interval Determined by CPU Processing (with Internal Clock Operation)
  202. Interval Determined by CPU Processing (with External Clock Operation)
  203. CHAPTER 15 VFD CONTROLLER/DRIVER
  204. VFD Controller Operation Timing in Display Mode 1 (DSPM05 = 0)
  205. VFD Controller/Driver Configuration
  206. VFD Controller/Driver Control Registers
  207. Format of Display Mode Register 2
  208. One-display period and cut width
  209. Selecting Display Mode
  210. Display Mode and Display Output
  211. Display Data Memory
  212. Key Scan Flag and Key Scan Data
  213. Light Leakage of VFD
  214. Display Examples
  215. Segment type (display mode 1: DSPM05 = 0)
  216. Dot type (display mode 1: DSPM05 = 0)
  217. Relationship Between Display Data Memory Contents and Segment Outputs in 35-Segment x 16-Digit Display Mode
  218. Display Data Memory Configuration and Data Reading Order (Display Mode 2)
  219. Grid Driving Timing
  220. Calculating Total Power Dissipation
  221. Relationship Between Display Data Memory Contents and Segment Outputs in 10-Segment x 11-Digit Display Mode
  222. CHAPTER 16 INTERRUPT AND TEST FUNCTIONS
  223. Interrupt Sources and Configuration
  224. Basic Configuration of Interrupt Function
  225. Interrupt Function Control Registers
  226. Format of Interrupt Request Flag Register
  227. Format of Interrupt Mask Flag Register
  228. Format of Priority Specification Flag Register
  229. Noise Eliminator I/O Timing (When Rising Edge Is Detected)
  230. Format of Program Status Word
  231. Interrupt Servicing Operations
  232. Non-Maskable Interrupt Request Acknowledgment Flowchart
  233. Non-Maskable Interrupt Request Acknowledgment Operation
  234. Maskable interrupt request acknowledgment operation
  235. Interrupt Request Acknowledge Processing Algorithm
  236. Software interrupt request acknowledgment operation
  237. Multiple interrupt servicing
  238. Multiple Interrupt Servicing Example
  239. Interrupt request hold
  240. Test Functions
  241. Test input signal acknowledgment operation
  242. CHAPTER 17 STANDBY FUNCTION
  243. Standby function control register
  244. Standby Function Operations
  245. HALT Mode Release by Interrupt Request Generation
  246. HALT Mode Release by RESET Input
  247. STOP mode
  248. STOP Mode Release by Interrupt Request Generation
  249. STOP Mode Release by RESET Input
  250. CHAPTER 18 RESET FUNCTION
  251. Timing of Reset by RESET Input
  252. Hardware Status After Reset
  253. CHAPTER 19 µ PD78P0208
  254. Internal Memory Size Switching Register
  255. Format of Internal Memory Size Switching Register (IMS)
  256. Internal Expansion RAM Size Switching Register
  257. PROM Programming
  258. PROM write procedure
  259. Page Program Mode Timing
  260. Byte Program Mode Flowchart
  261. Byte Program Mode Timing
  262. PROM read procedure
  263. Screening of One-Time PROM Version
  264. CHAPTER 20 INSTRUCTION SET
  265. Conventions
  266. Description of "operation" column
  267. Operation List
  268. Instructions Listed by Addressing Type
  269. APPENDIX A DIFFERENCES BETWEEN µ PD78044H, 780228, AND 780208 SUBSERIES
  270. APPENDIX B DEVELOPMENT TOOLS
  271. B-1 Configuration of Development Tools
  272. B.1 Software Package
  273. B.3 Control Software
  274. B.4 PROM Programming Tools
  275. B.5 Debugging Tools (Hardware)
  276. B.5.2 When using in-circuit emulator IE-78001-R-A
  277. B.6 Debugging Tools (Software)
  278. B.7 Embedded Software
  279. B.8 Method for Upgrading from Former In-Circuit Emulator for 78K/0 Series to IE-78001-R-A
  280. B.9 Conversion Socket (EV-9200GF-100) Package Drawing and Recommended Footprint
  281. B-3 Recommended Footprint for EV-9200GF-100 (for Reference Purposes only)
  282. B.10 Notes on Target System Design
  283. B-5 Connection Conditions of Target System (When NP-100GF-TQ Is Used)
  284. APPENDIX C REGISTER INDEX
  285. C.2 Register Index (by Register Symbol)
  286. APPENDIX D REVISION HISTORY
/ 418
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This manual is suitable for:
mPD780204mPD780204AmPD780205mPD780205AmPD780206mPD780208 SubseriesmPD78P0208
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