CHAPTER 14 SERIAL INTERFACE CHANNEL 1297User’s Manual U11302EJ4V0UM(a) When automatic transmit/receive function is performed using an internal clockThe internal clock operation is selected when bit 1 (CSIM11) of serial operating mode register 1(CSIM1) is set to 1.In this case, the interval is determined as follows by CPU processing.When bit 7 (ADTI7) of the automatic data transmit/receive interval specification register (ADTI) is setto 0, the interval is determined by CPU processing. When ADTI7 is set to 1, the interval is determinedby the contents of ADTI or by CPU processing, whichever is greater.For the interval determined by ADTI, see Figure 14-5 Format of Automatic Data Transmit/ReceiveInterval Specification Register.Table 14-3. Interval Determined by CPU Processing (with Internal Clock Operation)CPU Processing IntervalWhen using multiplication instruction MAX. (2.5T SCK , 13T CPU )When using division instruction MAX. (2.5T SCK , 20T CPU )External access 1-wait mode MAX. (2.5T SCK , 9T CPU )Other than above MAX. (2.5T SCK , 7T CPU )T SCK : 1/f SCKf SCK : Serial clock frequencyT CPU : 1/f CPUf CPU : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of theprocessor clock control register (PCC))MAX. (a, b) : a or b, whichever is greaterFigure 14-24. Operation Timing When Automatic Transmit/ReceiveFunction Is Operating with Internal Clockf X : Main system clock oscillation frequencyf CPU : CPU clock (set by bits 0 to 2 (PCC0 to PCC2) of the processor clock control register (PCC))T CPU : 1/f CPUT SCK : 1/f SCKf SCK : Serial clock frequencyf Xf CPU(n = 1)SCK1SO1SI1T CPUT SCK IntervalD7 D6 D5 D4 D3 D2 D1 D0D7 D6 D5 D4 D3 D2 D1 D0
