NXP Semiconductors MPC5777M Datasheet

Also see for MPC5777M: Safety manual

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NXP Semiconductors MPC5777M Datasheet Manual pdf 1 page image

NXP SemiconductorsData Sheet: Technical DataDocument Number: MPC5777MRev. 6, 06/2016NXP reserves the right to change the detail specifications as may be required to permitimprovements in the design of its products.MPC5777M416 TEPBGA27mm x 27 mm512 TEPBGA25 mm x 25 mm• Three main CPUs, single issue, 32-bit CPU core complexes(e200z7), one of which is a dedicated lockstep core.– Power Architecture ® embedded specificationcompliance– Instruction set enhancement allowing variable lengthencoding (VLE), encoding a mix of 16-bit and 32-bitinstructions, for code size footprint reduction– Single-precision floating point operations– 16 KB Local instruction RAM and 64 KB local dataRAM– 16 KB I-Cache and 4 KB D-Cache• I/O Processor, dual issue, 32-bit CPU core complex(e200z4), with– Power Architecture embedded specification compliance– Instruction set enhancement allowing variable lengthencoding (VLE), encoding a mix of 16-bit and 32-bitinstructions, for code size footprint reduction– Single-precision floating point operations– Lightweight Signal Processing Auxiliary ProcessingUnit (LSP APU) instruction support for digital signalprocessing (DSP)– 16 KB Local instruction RAM and 64 KB local dataRAM– 8 KB I-Cache• 8640 KB on-chip flash– Supports read during program and erase operations, andmultiple blocks allowing EEPROM emulation• 404 KB on-chip general-purpose SRAM including 64 KBstandby RAM (+ 192 KB data RAM included in theCPUs). Of this 404 KB, 64 KB can be powered by aseparate supply so the contents of this portion can bepreserved when the main MCU is powered down.• Multichannel direct memory access controllers (eDMA): 2x 64 channels per eDMA (128 channels total)• Triple Interrupt controller (INTC)– Dual phase-locked loops with stable clock domain forperipherals and FM modulation domain forcomputational shell• Dual crossbar switch architecture for concurrent access toperipherals, flash, or RAM from multiple bus masters withend-to-end ECC• Hardware Security Module (HSM) to provide robustintegrity checking of flash memory• System Integration Unit Lite (SIUL)• Boot Assist Module (BAM) supports factory programmingusing serial bootload through ‘UART Serial Boot ModeProtocol’. Physical interface (PHY) can be:– UART/LIN– CAN• GTM104 — generic timer module• Enhanced analog-to-digital converter system with– Twelve separate 12-bit SAR analog converters– Ten separate 16-bit Sigma-Delta analog converters• Eight deserial serial peripheral interface (DSPI) modules• Two Peripheral Sensor Interface (PSI5) controllers• Three LIN and three UART communication interface(LINFlexD) modules (6 total)– LINFlexD_0 is a Master/Slave– LINFlexD_1, LINFlexD_2, LINFlexD_14,LINFlexD_15, and LINFlexD_16 are Masters• Four modular controller area network (MCAN) modulesand one time-triggered controller area network(M-TTCAN)• External Bus Interface (EBI)– Dual routing of accesses to EBI– Access path determined by access address– Access path downstream of PFLASH controller– Allows EBI accesses to share buffer and prefetchcapabilities of internal flash– Allows internal flash accesses to be remapped tomemories connected to EBIMPC5777M MicrocontrollerData Sheet