MPC5777M Microcontroller Data Sheet, Rev. 6Electrical characteristicsNXP Semiconductors843.15.6 Flash memory AC timing specifications3.15.7 Flash read wait state and address pipeline control settingsTable 45 describes the recommended RWSC and APC settings at various operating frequencies based on specified intrinsicflash access times of the C55FMC array at 150 °C.Table 44. Flash memory AC timing specifications (characterized but not tested)Symbol Characteristic Min Typical Max Unitst psus Time from setting the MCR-PSUS bit until MCR-DONE bitis set to a 1.— 7 plus foursystemclockperiods9.1 plusfoursystemclockperiodsμst esus Time from setting the MCR-ESUS bit until MCR-DONE bitis set to a 1.— 16 plusfoursystemclockperiods20.8 plusfoursystemclockperiodsμst res Time from clearing the MCR-ESUS or PSUS bit withEHV = 1 until DONE goes low.— — 100 nstdone Time from 0 to 1 transition on the MCR-EHV bit initiating aprogram/erase until the MCR-DONE bit is cleared.— — 5 nstdones Time from 1 to 0 transition on the MCR-EHV bit aborting aprogram/erase until the MCR-DONE bit is set to a 1.— 16 plusfoursystemclockperiods20.8 plusfoursystemclockperiodsμstdrcv Time to recover once exiting low power mode. 16 plussevensystemclockperiods— 45 plussevensystemclockperiodsμstaistart Time from 0 to 1 transition of UT0-AIE initiating a MarginRead or Array Integrity until the UT0-AID bit is cleared.This time also applies to the resuming from a suspend orbreakpoint by clearing AISUS or clearing NAIBP— — 5 nstaistop Time from 1 to 0 transition of UTO-AIE initiating an ArrayIntegrity abort until the UT0-AID bit is set. This time alsoapplies to the UT0-AISUS to UT0-AID setting in the eventof a Array Integrity suspend request.— — 80plus fifteensystemclockperiodsnstmrstop Time from 1 to 0 transition of UTO-AIE initiating a MarginRead abort until the UT0-AID bit is set. This time alsoapplies to the UT0-AISUS to UT0-AID setting in the eventof a Margin Read suspend request.10.36plus foursystemclockperiods— 20.42plus foursystemclockperiodsμs