NXP Semiconductors MPC5777M Datasheet

Also see for MPC5777M: Safety manual

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NXP Semiconductors MPC5777M Datasheet Manual pdf 117 page image

Electrical characteristicsMPC5777M Microcontroller Data Sheet, Rev. 6NXP Semiconductors 1173.16.4.3 RxD3.16.5 PSI5 timingThe following table describes the PSI5 timing.3.16.6 UART timingUART channel frequency support is shown in the following table.Table 66. RxD input characteristics 11 FlexRay RxD timing is valid for Automotive input levels with hysteresis enabled (hysteresis permanently enabled inAutomotive input levels) and CMOS input levels with hysteresis disabled, 4.5 V  VDD_HV_IO  5.5 V for both cases.Symbol CharacteristicValueUnitMin MaxC_CCRxD CC Input capacitance on RxD pin — 7 pFuCCLogic_1 CC Threshold for detecting logic high 35 70 %uCCLogic_0 CC Threshold for detecting logic low 30 65 %dCCRxD01 CC Sum of delay from actual input to the D input of the firstFF, rising edge — 10 nsdCCRxD10 CC Sum of delay from actual input to the D input of the firstFF, falling edge — 10 nsdCCRxAsymAccept15 CC Acceptance of asymmetry at receiving CC with 15 pFload –31.5 44 nsdCCRxAsymAccept25 CC Acceptance of asymmetry at receiving CC with 25 pFload –30.5 43 nsTable 67. PSI5 timingSymbol ParameterValueUnitMin Maxt MSG_DLY CC Delay from last bit of frame (CRC0) to assertionof new message received interrupt— 3 μstSYNC_DLY CC Delay from internal sync pulse to sync pulsetrigger at the SDOUT_PSI5_n pin— 2 μst MSG_JIT CC Delay jitter from last bit of frame (CRC0) toassertion of new message received interrupt— 1 cycles11 Measured in PSI5 clock cycles (PBRIDGEn_CLK on the device). Minimum PSI5 clock period is 20 ns.t SYNC_JIT CC Delay jitter from internal sync pulse to sync pulsetrigger at the SDOUT_PSI5_n pin— ±(1 PSI5_1μs_CLK +1 PBRIDGEn_CLK)cycles