NXP Semiconductors MPC5777M Datasheet

Also see for MPC5777M: Safety manual

Contents

NXP Semiconductors MPC5777M Datasheet Manual pdf 109 page image

Electrical characteristicsMPC5777M Microcontroller Data Sheet, Rev. 6NXP Semiconductors 109Figure 39. DSPI Slave Mode - Modified transfer format timing (MFTE = 0/1) — CPHA = 13.16.3 FEC timingThe FEC provides both MII and RMII interfaces in the 416 TEPBGA and 512 TEPBGA packages, and the MII and RMIIsignals can be configured for either CMOS or TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.3.16.3.1 MII receive signal timing (RXD[3:0], RX_DV, RX_ER, and RX_CLK)The receiver functions correctly up to a RX_CLK maximum frequency of 25 MHz +1%. There is no minimum frequencyrequirement. The system clock frequency must be at least equal to or greater than the RX_CLK frequency.Table 58. MII receive signal timing 11 All timing specifications are referenced from RX_CLK = 1.4 V to the valid input levels, 0.8 V and 2.0 V.Symbol CharacteristicValueUnitMin MaxM1 CC RXD[3:0], RX_DV, RX_ER to RX_CLK setup 5 — nsM2 CC RX_CLK to RXD[3:0], RX_DV, RX_ER hold 5 — nsM3 CC RX_CLK pulse width high 35% 65% RX_CLK periodM4 CC RX_CLK pulse width low 35% 65% RX_CLK periodLast DataLast DataSINSOUTSSFirst DataFirst DataDataDataSCK InputSCK Input(CPOL=0)(CPOL=1)t A t DISt SUIt HIt SUOt HO