NXP Semiconductors MPC5777M Datasheet

Also see for MPC5777M: Safety manual

Contents

NXP Semiconductors MPC5777M Datasheet Manual pdf 85 page image

Electrical characteristicsMPC5777M Microcontroller Data Sheet, Rev. 6NXP Semiconductors 853.16 AC specificationsAll AC timing specifications are valid up to 150 °C, except where explicitly noted.3.16.1 Debug and calibration interface timing3.16.1.1 JTAG interface timingTable 45. Flash Read Wait State and Address Pipeline Control CombinationsFlash Frequency RWSC setting APC setting0 MHz < fFLASH  33 MHz 0 033 MHz < fFLASH  100 MHz 2 1100 MHz < fFLASH  133 MHz 3 1133 MHz < fFLASH  167 MHz 4 1167 MHz < fFLASH  200 MHz 5 2Table 46. JTAG pin AC electrical characteristics1,21 These specifications apply to JTAG boundary scan only. See Table 47 for functional specifications.2 JTAG timing specified at V DD_HV_IO_JTAG = 4.0 V to 5.5 V, and maximum loading per pad type as specified in theI/O section of the data sheet.# Symbol CharacteristicValueUnitMin Max1 tJCYC CC TCK cycle time 100 — ns2 t JDC CC TCK clock pulse width 40 60 %3 t TCKRISE CC TCK rise and fall times (40%–70%) — 3 ns4 t TMSS, t TDIS CC TMS, TDI data setup time 5 — ns5 t TMSH, t TDIH CC TMS, TDI data hold time 5 — ns6 tTDOV CC TCK low to TDO data valid — 16 33 Timing includes TCK pad delay, clock tree delay, logic delay and TDO output pad delay.ns7 tTDOI CC TCK low to TDO data invalid 0 — ns8 tTDOHZ CC TCK low to TDO high impedance — 15 ns9 t JCMPPW CC JCOMP assertion time 100 — ns10 t JCMPS CC JCOMP setup time to TCK low 40 — ns11 tBSDV CC TCK falling edge to output valid — 6004 ns12 t BSDVZ CC TCK falling edge to output valid out of high impedance — 600 ns13 t BSDHZ CC TCK falling edge to output high impedance — 600 ns14 t BSDST CC Boundary scan input valid to TCK rising edge 15 — ns15 t BSDHT CC TCK rising edge to boundary scan input invalid 15 — ns