Xilinx AC701 User Manual

Also see for AC701: User guide Manual User guide User guide

Xilinx AC701 User Manual Manual pdf 24 page image

24 www.xilinx.com AC701 Evaluation BoardUG952 (v1.4) August 6, 2019Chapter 1: AC701 Evaluation Board FeaturesThe JTAG connectivity on the AC701 board allows a host computer to download bitstreams to theFPGA using Xilinx software tools. In addition, the JTAG connector allows debug tools or a softwaredebugger to access the FPGA. Xilinx software tools can also indirectly program the Quad SPI flashmemory. To accomplish this, Xilinx software configures the FPGA with a temporary design toaccess and program the Quad SPI flash memory device. The JTAG circuit is shown in Figure 1-9.Clock GenerationThere are three clock sources available for the FPGA logic on the AC701 board (see Table 1-8).X-Ref Target - Figure 1-9Figure 1-9: JTAG CircuitUG952_c1_09_101512JTAG_TDIFMC_TDI_BUFFPGA_TDOFPGA_TMS_BUFFPGA_TCK_BUFFPGA_TDI_BUFFMC1_TDO_FPGA_TDIFMC1_HPC_TMS_BUFFMC1_HPC_PRSNT_M2C_BJTAG_TMSJTAG_TCKJTAG_TDOFMC1_HPC_TCK_BUFFMC1 HPCConnectorTDITDOJ30TMSTCKPRSNT_LVCC3V3Artix-7FPGATDIN16TDOU1TMSTCKDigilentUSB-JTAGModuleTMSTDISN74LV541ABufferU19R95 15ΩU26R96 15ΩR94 15ΩTCKTDOTMSTDIJ4TCKTDOJTAGHeaderVCC3V3VCC3V3U27Bank 0Bank 14Table 1-8: AC701 Board Clock SourcesFPGAPin (U1)Schematic NetName I/O Standard ClockReference Pin DescriptionR3 SYSCLK_P LVDS_25 U51 4 SiT9102 2.5V LVDS 200 MHz Fixed Frequency Oscillator(SiTime). See System Clock Source.P3 SYSCLK_N LVDS_25 5Send Feedback