Xilinx AC701 User Manual

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Xilinx AC701 User Manual Manual pdf 49 page image

AC701 Evaluation Board www.xilinx.com 49UG952 (v1.4) August 6, 2019Feature DescriptionsTable 1-21 lists the connections between the FPGA and the LCD header. If the LCD is not installed,the J23 pins listed in Table 1-21 can be used for GPIO.For the Displaytech S162DBABC LCD data sheet, see [Ref 23].I2C Bus Switch[Figure 1-2, callout 19]The AC701 board implements a single I2C port on FPGA Bank 14 (IIC_SDA_MAIN, FPGA pinK25 and IIC_SCL_MAIN, FPGA pin N18), which is routed through a Texas Instruments PCA95481-to-8 channel I2C switch (U52). The I2C switch can operate at speeds up to 400 kHz. The U52 busswitch at I2C address 0x74/0b01110100 must be addressed and configured to select the desiredtarget downstream device.The AC701 board I2C bus topology is shown in Figure 1-29.User applications that communicate with devices on one of the downstream I2C buses must first setup a path to the desired bus through the U52 bus switch at I2C address 0x74/0b01110100.Table 1-21: FPGA to LCD Header ConnectionsFPGA Pin (U1) Schematic Net Name I/O Standard LCD Header Pin (J23)L25 LCD_DB4_LS LVCMOS33 4M24 LCD_DB5_LS LVCMOS33 3M25 LCD_DB6_LS LVCMOS33 2L22 LCD_DB7_LS LVCMOS33 1L24 LCD_RW_LS LVCMOS33 10L23 LCD_RS_LS LVCMOS33 11L20 LCD_E_LS LVCMOS33 9X-Ref Target - Figure 1-29Figure 1-29: I2C Bus TopologyPCA954812C 1-to-8Bus SwitchCH7 - SI5324_SDA/SCLU52IIC_SDA/SCL_MAINCH6 - IIC_SDA/SCL_DDR3CH5 - IIC_SDA/SCL_HDMICH4 - SFP_IIC_SDA/SCLCH3 - EEPROM_IIC_SDA/SCLCH2 - (NOT USED)CH1 - FMC_HPC_IIC_SDA/SCLCH0 - USER_CLK_SDL/SCLFPGABank 14(3.3V)0x74U1UG952_C1_27_100312Send Feedback