Xilinx AC701 User Manual

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Xilinx AC701 User Manual Manual pdf 38 page image

38 www.xilinx.com AC701 Evaluation BoardUG952 (v1.4) August 6, 2019Chapter 1: AC701 Evaluation Board FeaturesPCI Express Edge Connector[Figure 1-2, callout 12]The 4-lane PCI Express edge connector performs data transfers at the rate of 2.5 GT/s for a Gen1application and 5.0 GT/s for a Gen2 application. The PCIe transmit and receive signal datapathshave a characteristic impedance of 85Ω ±10%. The PCIe clock is routed as a 100Ω differential pair.The 7 series FPGAs GTP transceivers are used for multi-gigabit per second serial interfaces.The XC7A200T-2FBG676C FPGA (-2 speed grade) included with the AC701 board supports up toGen2 x4.The PCIe clock is input from the edge connector. It is AC coupled to the FPGA through theMGTREFCLK0 pins of Quad 216. PCIE_CLK_Q0_P is connected to FPGA U1 pin F11, and the_N net is connected to pin E11. The PCI Express clock circuit is shown in Figure 1-20.PCIe lane width/size is selected using jumper J12 (Figure 1-21). The default lane size selection is4-lane (J12 pins 3 and 4) jumpered).Table 1-12 lists the PCIe edge connector connections.For more information, see the 7 Series FPGAs Integrated Block for PCI Express v3.0 Product Guide(PG054) [Ref 9].X-Ref Target - Figure 1-20Figure 1-20: PCI Express ClockX-Ref Target - Figure 1-21Figure 1-21: PCI Express Lane Size Select Jumper J12UG952_c1_18_100312PCI ExpressFour-LaneEdge connectorGNDGNDA15A13A14P1REFCLK+A12GNDC1880.01μF 25VX7RC1890.01μF 25VX7RPCIE_CLK_Q0_PPCIE_CLK_Q0_NPCIE_CLK_Q0_C_PPCIE_CLK_Q0_C_NOEREFCLK-UG952_c1_19_100312PCIE_PRSNT_BPCIE_PRSNT_X1PCIE_PRSNT_X4J121324Send Feedback