Xilinx SP601 User Manual
Also see for Spartan-6 FPGA Series: Getting startedUser guideDesign and pin planning guideUser guideUser guide
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Contents
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SP601 Hardware User Guide www.xilinx.com 11UG518 (v1.1) August 19, 2009Related Xilinx DocumentsBlock DiagramFigure 1-1 shows a high-level block diagram of the SP601 and its peripherals.Related Xilinx DocumentsPrior to using the SP601 Evaluation Board, users should be familiar with Xilinx resources.See the following locations for additional documentation on Xilinx tools and solutions:• ISE: www.xilinx.com/ise• Answer Browser: www.xilinx.com/support• Intellectual Property: www.xilinx.com/ipcenterX-Ref Target - Figure 1-1Figure 1-1: SP601 Features and BankingLEDsDIP SwitchGPIO HeaderFMC LPCExpansion Connector10/100/1000Ethernet GMIISpartan-6XC6SLX16U1Parallel FlashUSBJTAG ConnectorPushbuttonsDDR2Differential ClockClock SocketSMA ClockIIC EEPROMand HeaderMODEDIP SwitchSPI x4 orExternal ConfigUSB UARTUG518_01_070809DEDBank 02.5 VBank 31.8VBank 12.5VBank 22.5V |
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