Xilinx SP601 User Manual

Also see for Spartan-6 FPGA Series: Getting started User guide Design and pin planning guide User guide User guide

Xilinx SP601 User Manual Manual pdf 13 page image

SP601 Hardware User Guide www.xilinx.com 13UG518 (v1.1) August 19, 2009Detailed Description1. Spartan-6 XC6SLX16-2CSG324 FPGAA Xilinx Spartan-6 XC6SLX16-2CSG324 FPGA is installed on the Embedded DevelopmentBoard.ConfigurationThe SP601 supports configuration in the following modes:• Master SPI x4• Master SPI x4 with off-board device• BPI• JTAG (using the included USB-A to Mini-B cable)For details on configuring the FPGA, see “Configuration Options.”I/O Voltage RailsThere are four available banks on the LX16-CS324 device. Banks 0, 1, and 2 are connectedfor 2.5V I/O. Bank 3 is used for the 1.8V DDR2 component memory interface of Spartan-6FPGA’s hard memory controller. The voltage applied to the FPGA I/O banks used by theSP601 board is summarized in Table 1-2.9 VITA 57.1 FMC-LPCconnectorLVDS signals, clocks, PRSNT 610 LEDs Ethernet PHY Status 711 LED, Header FPGA Awake LED, Suspend Header 812 LEDs FPGA INIT, DONE 913LED User I/O (active-High) 9DIP Switch User I/O (active-High) 9Pushbutton User I/O, CPU_RESET (active-High) 912-pin (8 I/O) Header 6 pins x 2 male header with 8 I/Os(active-High)1014 Pushbutton FPGA_PROG_B 915 USB JTAG Cypress USB to JTAG download cablelogic14, 1516 Onboard Power Power Management 11,12,13Table 1-1: SP601 Features (Cont’d)Number Feature Notes SchematicPageTable 1-2: I/O Voltage Rail of FPGA BanksFPGA Bank I/O Voltage Rail0 2.5V1 2.5V