Xilinx SP601 User Manual

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Xilinx SP601 User Manual Manual pdf 23 page image

SP601 Hardware User Guide www.xilinx.com 23UG518 (v1.1) August 19, 2009Detailed Description5. 10/100/1000 Tri-Speed Ethernet PHYThe SP601 uses the onboard Marvell Alaska PHY device (88E1111) for Ethernetcommunications at 10, 100, or 1000 Mb/s. The board supports a GMII/MII interface fromthe FPGA to the PHY. The PHY connection to a user-provided Ethernet cable is through aHalo HFJ11-1G01E RJ-45 connector with built-in magnetics.On power-up, or on reset, the PHY is configured to operate in GMII mode with PHYaddress 0b00111 using the settings shown in Table 1-8. These settings can be overwrittenvia software commands passed over the MDIO interface.Table 1-8: PHY Configuration PinsPin Connection onBoardBit[2]Definition and ValueBit[1]Definition and ValueBit[0]Definition and ValueCFG0 VCC 2.5V PHYADR[2] = 1 PHYADR[1] = 1 PHYADR[0] = 1CFG1 Ground ENA_PAUSE = 0 PHYADR[4] = 0 PHYADR[3] = 0CFG2 VCC 2.5V ANEG[3] = 1 ANEG[2] = 1 ANEG[1] = 1CFG3 VCC 2.5V ANEG[0] = 1 ENA_XC = 1 DIS_125 = 1CFG4 VCC 2.5V HWCFG_MD[2] = 1 HWCFG_MD[1] = 1 HWCFG_MD[0] = 1CFG5 VCC 2.5V DIS_FC = 1 DIS_SLEEP = 1 HWCFG_MD[3] = 1CFG6 PHY_LED_RX SEL_BDT = 0 INT_POL = 1 75/50 OHM = 0Table 1-9: PHY ConnectionsFPGA U1Pin Schematic Netname U3 M88E111P16 PHY_MDIO 33N14 PHY_MDC 35J13 PHY_INT 32L13 PHY_RESET 36M13 PHY_CRS 115L14 PHY_COL 114L16 PHY_RXCLK 7P17 PHY_RXER 8N18 PHY_RXCTL_RXDV 4M14 PHY_RXD0 3U18 PHY_RXD1 128U17 PHY_RXD2 126T18 PHY_RXD3 125T17 PHY_RXD4 124N16 PHY_RXD5 123N15 PHY_RXD6 121