Xilinx SP601 User Manual

Also see for Spartan-6 FPGA Series: Getting started User guide Design and pin planning guide User guide User guide

Xilinx SP601 User Manual Manual pdf 42 page image

42 www.xilinx.com SP601 Hardware User GuideUG518 (v1.1) August 19, 2009Chapter 1: SP601 Evaluation BoardConfiguration OptionsThe FPGA on the SP601 Evaluation Board can be configured by the following methods:• “3. SPI x4 Flash,” page 18• “4. Linear Flash BPI,” page 20• “JTAG Configuration,” page 42For more information, refer to the Spartan-6 FPGA Configuration User Guide. [Ref 2]JTAG ConfigurationJTAG configuration is provided through onboard USB-to-JTAG configuration logic wherea computer host accesses the SP601 JTAG chain through a Type-A (computer host side) toType-Mini-B (SP601 side) USB cable.The JTAG chain of the board is illustrated in Figure 1-31. JTAG configuration is allowableat any time under any mode pin setting. JTAG initiated configuration takes priority overthe mode pin settings.FMC bypass jumper J4 must be connected between pins 1-2 for JTAG access to the FPGAon the basic SP601 board, as shown in Figure 1-31. When the VITA 57.1 FMC expansionconnector is populated with an expansion module that has a JTAG chain, then jumper J4must be set to connect pins 2-3 in order to include the FMC expansion module's JTAGchain in the main SP601 JTAG chain.Table 1-23: Mode Pin Settings (M2 = 0)Mode Pins (M1, M0) Configuration Mode00 Master Byte Peripheral Interface (BPI)01 Master SPI x1, x2, or x410 Not implemented on SP60111 Not implemented on SP601X-Ref Target - Figure 1-31Figure 1-31: JTAG ChainFMC LPC ExpansionTDITDITDOTDOJ1U1J10J4FPGAUSB Mini-BConnectorUG518_31_070809*Default jumper setting excludes FMC.To include FMC, jumper pins 2-3.1