Xilinx ZC706 User Manual

Also see for ZC706: Manual

Contents

ZC706 Evaluation Board User Guide www.xilinx.com 21UG954 (v1.5) September 10, 2015Feature DescriptionsB11 PL_DDR3_D61 SSTL15 182 DQ61C14 PL_DDR3_D62 SSTL15 192 DQ62B14 PL_DDR3_D63 SSTL15 194 DQ63J3 PL_DDR3_DM0 SSTL15 11 DM0F2 PL_DDR3_DM1 SSTL15 28 DM1E1 PL_DDR3_DM2 SSTL15 46 DM2C2 PL_DDR3_DM3 SSTL15 63 DM3L12 PL_DDR3_DM4 SSTL15 136 DM4G14 PL_DDR3_DM5 SSTL15 153 DM5C16 PL_DDR3_DM6 SSTL15 170 DM6C11 PL_DDR3_DM7 SSTL15 187 DM7K2 PL_DDR3_DQS0_N DIFF_SSTL15 10 DQS0_NK3 PL_DDR3_DQS0_P DIFF_SSTL15 12 DQS0_PH1 PL_DDR3_DQS1_N DIFF_SSTL15 27 DQS1_NJ1 PL_DDR3_DQS1_P DIFF_SSTL15 29 DQS1_PD5 PL_DDR3_DQS2_N DIFF_SSTL15 45 DQS2_NE6 PL_DDR3_DQS2_P DIFF_SSTL15 47 DQS2_PA4 PL_DDR3_DQS3_N DIFF_SSTL15 62 DQS3_NA5 PL_DDR3_DQS3_P DIFF_SSTL15 64 DQS3_PK8 PL_DDR3_DQS4_N DIFF_SSTL15 135 DQS4_NL8 PL_DDR3_DQS4_P DIFF_SSTL15 137 DQS4_PF12 PL_DDR3_DQS5_N DIFF_SSTL15 152 DQS5_NG12 PL_DDR3_DQS5_P DIFF_SSTL15 154 DQS5_PE17 PL_DDR3_DQS6_N DIFF_SSTL15 169 DQS6_NF17 PL_DDR3_DQS6_P DIFF_SSTL15 171 DQS6_PA15 PL_DDR3_DQS7_N DIFF_SSTL15 186 DQS7_NB15 PL_DDR3_DQS7_P DIFF_SSTL15 188 DQS7_PG7 PL_DDR3_ODT0 SSTL15 116 ODT0C9 PL_DDR3_ODT1 SSTL15 120 ODT1G17 PL_DDR3_RESET_B SSTL15 30 RESET_BJ11 PL_DDR3_S0_B SSTL15 114 S0_BH8 PL_DDR3_S1_B SSTL15 121 S1_BM10 PL_DDR3_TEMP_EVENTSSTL15 198 EVENT_BF7 PL_DDR3_WE_B SSTL15 113 WE_BTable 1-4: DDR3 SODIMM Socket J1 Connections to the XC7Z045 AP SoC (Cont’d)XC7Z045 (U1)Pin Net Name I/O Standard DDR3 SODIMM Memory J1Pin Number Pin NameSend Feedback