Xilinx ZC706 User Manual

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ZC706 Evaluation Board User Guide www.xilinx.com 35UG954 (v1.5) September 10, 2015Feature DescriptionsThe system clock source is an LVDS 200 MHz oscillator at U64. It is wired to a multi-regionclock capable (MRCC) input on programmable logic (PL) bank 34. The signal pair is namedSYSCLK_P and SYSCLK_N and each signal is connected to U1 (pins H9 and G9, respectively)on the XC7Z045 AP SoC.• Oscillator: SiTime SiT9102AI-243N25E200.00000 (200 MHz)• Frequency tolerance: 50 ppm• LVDS Differential OutputThe system clock circuit is shown in Figure 1-11.For more details, see the SiTime SiT9102 data sheet [Ref 20].Programmable User Clock[Figure 1-2, callout 8]The ZC706 evaluation board has a programmable low-jitter 3.3V LVDS differential oscillator(U37) connected to the MRCC inputs of bank 10. This USRCLK_P and USRCLK_N clock signalpair is connected to XC7Z045 AP SoC U1 pins AF14 and AG14, respectively. On power-upthe user clock defaults to an output frequency of 156.250 MHz. User applications canchange the output frequency within the range of 10 MHz to 810 MHz through an I 2 Cinterface. Power cycling the ZC706 evaluation board reverts the user clock to the defaultfrequency of 156.250 MHz.• Programmable Oscillator: Silicon Labs Si570BAB0000544DG (10 MHz–810 MHz)• Frequency tolerance: 50 ppm• LVDS Differential OutputX-Ref Target - Figure 1-11Figure 1-11: System Clock SourceUG954_c1_11_041113GNDVCC2V5SIT9102200 MHzOscillatorOENCGNDVCCOUT_BOUT123654U64R322100Ω1/20W 5% SYSCLK_PSYSCLK_NC890.1 μF 10VX5R1221Send Feedback