Xilinx ZC706 User Manual

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ZC706 Evaluation Board User Guide www.xilinx.com 50UG954 (v1.5) September 10, 2015Feature DescriptionsTable 1-22 lists the USB connections between the XC7Z045 AP SoC PS Bank 501 and theCP2103 UART bridge.Refer to the Silicon Labs website for technical information on the CP2103GM and the VCPdrivers [Ref 21].For additional information on the Zynq-7000 AP SoC device UART controller, see Zynq-7000All Programmable SoC Overview (DS190) and Zynq-7000 All Programmable SoC TechnicalReference Manual (UG585).HDMI Video Output[Figure 1-2, callout 18]The ZC706 evaluation board provides a high-definition multimedia interface (HDMI®)video output using an Analog Devices ADV7511KSTZ-P HDMI transmitter at U53. The HDMItransmitter U53 is connected to the XC7Z045 AP SoC PL-side banks 12 and 13 and its outputis provided on a Molex 500254-1927 HDMI type-A receptacle at P1. The ADV7511 supports1080P 60Hz, YCbCr 4:4:4 encoding via 24-bit input data mapping.The ZC706 evaluation board supports the following HDMI device interfaces:• 24 data lines• Independent VSYNC, HSYNC• Single-ended input CLK• Interrupt Out pin to XC7Z045 AP SoCTable 1-21: USB Connector J21 Pin Assignments and Signal DefinitionsUSB Connector (J21) Net Name Description CP2103GM (U52)Pin Name Pin Name1 VBUS USB_UART_VBUS +5V VBUS Powered 7 REGIN8 VBUS2 D_N USB_UART_D_N Bidirectional differential serial data (N-side) 4 D –3 D_P USB_UART_D_P Bidirectional differential serial data (P-side) 3 D +5 GND USB_UART_GND Signal ground 2 GND129 CNR_GNDTable 1-22: XC7Z045 AP SoC to CP2103 ConnectionsXC7045 AP SoC (U1) Schematic NetNameCP2103GM Device (U52)Pin Name Bank PIN Function Direction IOSTANDARD PIN Function DirectionPS_MIO48 501 C19 TX Output LVCMOS18 USB_UART_RX 24 RXD InputPS_MIO49 501 D18 RX Input LVCMOS18 USB_UART_TX 25 TXD OutputSend Feedback