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NEC V850/SA1 mPD70F3017Y manuals

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V850/SA1 mPD70F3017Y

Brand: NEC | Category: Microcontrollers
Table of contents
  1. Table Of Contents
  2. Table Of Contents
  3. Table Of Contents
  4. Table Of Contents
  5. Table Of Contents
  6. Table Of Contents
  7. Table Of Contents
  8. Table Of Contents
  9. Table Of Contents
  10. Table Of Contents
  11. Table Of Contents
  12. Table Of Contents
  13. CHAPTER 1 INTRODUCTION
  14. Application Fields
  15. Pin Configuration (Top View)
  16. Function Blocks
  17. On-chip units
  18. CHAPTER 2 PIN FUNCTIONS
  19. Pin States
  20. Description of Pin Functions
  21. Pins' I/O Circuit Types and Handling When Not Used
  22. Pins' I/O Circuits
  23. CHAPTER 3 CPU FUNCTIONS
  24. CPU Register Set
  25. Program register set
  26. System register set
  27. Operation Modes
  28. Address Space
  29. Image (virtual address space)
  30. Wrap-around of CPU address space
  31. Memory map
  32. Area
  33. Interrupt/Exception Table
  34. External Memory Area (when expanded to 64 K, 256 K, or 1 Mbytes)
  35. External Memory Area (when expanded to 4 Mbytes)
  36. External expansion mode
  37. Memory Expansion Mode Register (MM) Format
  38. Memory Address Output Mode Register (MAM) Format
  39. Recommended use of address space
  40. Recommended Memory Map (Flash Memory Internal Version)
  41. Peripheral I/O registers
  42. Specific registers
  43. CHAPTER 4 BUS CONTROL FUNCTION
  44. Control register
  45. Bus width
  46. Memory Block Function
  47. Wait Function
  48. External wait function
  49. Idle State Insertion Function
  50. Bus Hold Function
  51. Bus hold procedure
  52. Bus Timing
  53. Bus Priority
  54. Features
  55. Interrupt Source List
  56. Non-Maskable Interrupt
  57. Accepting operation
  58. Accepting Non-Maskable Interrupt Request
  59. Restore
  60. NP flag
  61. Edge detection function of NMI pin
  62. Maskable Interrupts
  63. Maskable Interrupt Processing
  65. Priorities of maskable interrupts
  66. Example of Interrupt Nesting Process
  67. Example of Processing Interrupt Requests Simultaneously Generated
  68. Interrupt control register (xxICn)
  69. In-service priority register (ISPR)
  70. Watchdog timer mode register (WDTM)
  71. Edge detection function
  72. Software Exception
  74. EP flag
  76. RETI Instruction Processing
  77. Priority Control
  78. Interrupt Latency Time
  79. CHAPTER 6 CLOCK GENERATION FUNCTION
  80. Clock Output Function
  81. Format of Power Saving Control Register (PSC)
  82. Power Saving Functions
  83. HALT mode
  84. Operating Statuses during HALT Mode
  85. IDLE mode
  86. Software STOP mode
  87. Oscillation Stabilization Time
  88. CHAPTER 7 TIMER/COUNTER FUNCTION
  89. Block Diagram of TM0 and TM1
  90. Configuration
  91. Valid Edge of TIn0 Pin and Capture Trigger of CRn0
  92. Timer 0, 1 Control Register
  93. Format of 16-Bit Timer Mode Control Register 0, 1 (TMC0, TMC1)
  94. Format of Capture/Compare Control Register 0, 1 (CRC0, CRC1)
  95. Format of 16-Bit Timer Output Control Register 0, 1 (TOC0, TOC1)
  96. Format of Prescaler Mode Register 0 (PRM0)
  97. Format of Prescaler Mode Register 1 (PRM1)
  98. Operation
  99. Configuration of Interval Timer
  100. PPG output operation
  101. Pulse width measurement
  102. Configuration for Pulse Width Measurement with Free Running Counter
  103. Control Register Settings for Measurement of Two Pulse Widths with Free Running Counter
  104. CRn1 Capture Operation with Rising Edge Specified
  105. Control Register Settings for Pulse Width Measurement by Restarting
  106. Operation as external event counter
  107. Operation to output square wave
  108. Control Register Settings in Square Wave Output Mode
  109. Operation to output one-shot pulse
  110. Control Register Settings for One-Shot Pulse Output with Software Trigger
  111. Timing of One-Shot Pulse Output Operation with Software Trigger
  112. Control Register Settings for One-Shot Pulse Output with External Trigger
  113. Cautions
  114. Timing after Changing Compare Register during Timer Count Operation
  115. Operation Timing of OVFn Flag
  116. bit Timer (TM2-TM5)
  118. Timer n control register
  119. Format of TM4, TM5 Timer Clock Selection Register 4 and 5 (TCL4, TCL5)
  120. Format of 8-Bit Timer Mode Control Register 2-5 (TMC2-TMC5)
  122. Operating as external event counter
  123. Operating as square wave output (8-bit resolution)
  124. Operating as 8-bit PWM output
  125. Timing of PWM Output
  126. Timing of Operation Based on CRn0 Transitions
  127. Cascade Connection Mode with 16-Bit Resolution
  129. CHAPTER 8 WATCH TIMER
  131. Watch Timer Control Register
  133. Operation as interval timer
  134. CHAPTER 9 WATCHDOG TIMER
  135. Runaway Detection Time for Watchdog Timer
  137. Format of Watchdog Timer Clock Selection Register (WDCS)
  138. Format of Watchdog Timer Mode Register (WDTM)
  140. Operating as interval timer
  141. Standby Function Control Register
  142. CHAPTER 10 SERIAL INTERFACE FUNCTION
  144. CSIn control registers
  145. Format of Serial Clock Selection Registers 0-2 (CSIS0-CSIS2)
  146. Operations
  147. Format of Serial Operation Mode Registers 0-2 (CSIM0-CSIM2)
  148. Timing of 3-wire Serial I/O Mode
  150. Format of IIC Control Register (IICC0)
  151. Format of IIC Status Register (IICS0)
  152. Format of IIC Clock Select Register (IICCL0)
  153. Pin Configuration Diagram
  154. Start Conditions
  155. Address
  156. Transfer Direction Specification
  157. ACK Signal
  158. Stop Condition
  159. Wait Signal
  160. Interrupt request (INTIIC0) generation timing and wait control
  161. Address match detection method
  162. Error detection
  163. Arbitration
  164. Arbitration Timing Example
  165. Wake up function
  166. Communication reservation
  167. Communication Reservation Timing
  168. Timing for Accepting Communication Reservations
  169. Communication Reservation Flow Chart
  170. Other cautions
  171. Communication operations
  172. Slave Operation Flow Chart
  173. Timing of data communication
  174. Asynchronous Serial Interface (UART0, UART1)
  175. Block Diagram of UARTn
  176. UARTn control registers
  177. Format of Asynchronous Serial Interface Mode Register 0, 1 (ASIM0, ASIM1)
  178. Format of Asynchronous Serial Interface Status Registers 0, 1 (ASIS0, ASIS1)
  179. Format of Baud Rate Generator Control Registers 0, 1 (BRGC0, BRGC1)
  180. Format of Baud Rate Generator Mode Control Registers 0, 1 (BRGMC0, BRGMC1)
  182. Asynchronous serial interface (UARTn) mode
  183. Relation between Main Clock and Baud Rate
  184. Error Tolerance (when k = 0), including Sampling Errors
  185. Format of Transmit/Receive Data in Asynchronous Serial Interface
  186. Timing of Asynchronous Serial Interface Transmit Completion Interrupt
  187. Timing of Asynchronous Serial Interface Receive Completion Interrupt
  188. Receive Error Timing
  189. Standby function
  190. CHAPTER 11 A/D CONVERTER
  191. Block Diagram of A/D Converter
  193. Control Registers
  194. Format of Analog Input Channel Specification Register (ADS)
  196. Basic Operation of A/D Converter
  197. Input voltage and conversion result
  198. A/D converter operation mode
  199. A/D Conversion by Hardware Start (with falling edge specified)
  200. A/D Conversion by Software Start
  201. Notes on Using A/D Converter
  202. Processing of Analog Input Pin
  203. A/D Conversion End Interrupt Generation Timing
  204. CHAPTER 12 DMA FUNCTIONS
  205. Format of DMA On-chip RAM Address Registers 0 to 2 (DRA0 to DRA2)
  206. Format of DMA Channel Control Registers 0 to 2 (DCHC0 to DCHC2)
  207. CHAPTER 13 REAL-TIME OUTPUT FUNCTION (RTO)
  209. RTO Control Registers
  210. Format of Real-Time Output Port Mode Register (RTPM)
  211. Format of Real-Time Output Port Control Register (RTPC)
  213. Usage
  214. CHAPTER 14 PORT FUNCTION
  215. Format of Port 0 Mode Register (PM0)
  216. Format of Rising Edge Enable Register (EGP0)
  217. Port 1
  218. Format of Port 1 Mode Register (PM1)
  219. Format of Pull-up Resistance Option Register 1 (PU1)
  220. Port 2
  221. Format of Port 2 Mode Register (PM2)
  222. Format of Pull-up Resistance Option Register 2 (PU2)
  223. Port 3
  224. Format of Port 3 Mode Register (PM3)
  225. Ports 4 and 5
  226. Port 6
  227. Format of Port 6 Mode Register (PM6)
  228. Ports 7 and 8
  229. Port 9
  230. Format of Port 9 Mode Register (PM9)
  231. Port 10
  232. Format of Port 10 Mode Register (PM10)
  233. Port 11
  234. Format of Port 11 (P11)
  235. Format of Port 11 Mode Register (PM11)
  236. Port 12
  237. Format of Port 12 Mode Register (PM12)
  238. Format of Port 12 Mode Control Register (PMC12)
  239. CHAPTER 15 RESET FUNCTION
  240. CHAPTER 16 FLASH MEMORY ( µ µ µ µ PD70F3017, 70F3017Y)
  241. Programming Environment
  242. Pin Connection
  243. RESET pin
  244. Programming Method
  245. Selection of communication mode
  246. Resources used
  247. APPENDIX A REGISTER INDEX
  248. APPENDIX B LIST OF INSTRUTION SET
  249. APPENDIX C INDEX
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