5-146 D60 LINE DISTANCE PROTECTION SYSTEM – INSTRUCTION MANUALSYSTEM SETUP CHAPTER 5: SETTINGS5UR firmware versions 7.0 and above have a 90-5 based R-SV implementation equivalent in structure and configuration tothat of the existing IEEE C37.118 implementation of firmware version 6.0, that is, synchrophasor data at rates up to 60 Hzfor metering and 120 Hz for protection class synchrophasors. The following two figures depict the general data flow for thegeneration of synchrophasor data for IEC 61850-90-5. In the first figure, when IEC 61850-90-5 is selected all real andvirtual sources are available for the IEC 61850-90-5 PMUs.The number of PMUs and aggregators vary by product, as outlined in the table.Table 5-18: PMU implementation by UR deviceThe figure shows an example of an N60 using four Logical Device PMUs (Logical Device 2 through 5) and four aggregators.The control blocks for the aggregators are located in LD1. A 64 character LDName setting is provided.Figure 5-75: N60 example for four logical device PMUsDepending on the applied filter, the synchrophasors that are produced by PMUs are classified as either P (protection) or M(Measurement) class synchrophasors. Synchrophasors available within the UR that have no filtering applied are classifiedas NONE, which within the standard is classified as PRES OR UNKNOWN under the Calculation Method - ClcMth. EachLogical Device PMU supports one MxxMMXU, MxxMSQI, PxxxMMXU , PxxxMSQI, NxxMMXU, and one NxxMSQI logical node.UR device Number ofPMUSNumber ofaggregatorsNumber ofanalog inputsCommentN60 6 4 16 1, 2, 4, or 6 PMUs can be usedC60 2 2 16D60, F60, G60, L30, L90, T60 1 1 16Precise time input to the relay from the international time standard, via either IRIG-B or PTP, is vital for correctsynchrophasor measurement and reporting. For IRIG-B, a DC level shift IRIG-B receiver must be used for the PMU tooutput proper synchrophasor values.
