CHAPTER 8: APPLICATION OF SETTINGS SERIES COMPENSATED LINESD60 LINE DISTANCE PROTECTION SYSTEM – INSTRUCTION MANUAL 8-118extra (series) asymmetry in addition to the fault (shunt) asymmetry. The positive-, negative- and zero-sequenceimpedances differ from each other and do not equal the impedance of the phase capacitors. Moreover, there can bemutual coupling between the sequence networks representing the series capacitor bank. This makes analytical analysis offault conditions burdensome. For setting calculations, however, it is justified to assume the zero-, positive-, and negative-sequence reactance of the capacitor bank equal the reactance of the actual (phase) capacitors. This represents a worst-case low-current fault scenario, when the steady-state effects of series compensation are most weighty.8.4.2 DistanceTraditionally, the reach setting of an underreaching distance function is set based on the net inductive impedancebetween the potential source of the relay and the far-end busbar, or location for which the zone must not overreach. Faultsbehind series capacitors on the protected and adjacent lines need to be considered for this purpose. For furtherillustration, a sample system shown in the figure is considered.Figure 8-2: Sample series-compensated systemAssuming 20% security margin, the underreaching zone is set as follows.At the Sending Bus, consider an external fault at F1 because the 5 Ω capacitor contributes to the overreaching effect. Anyfault behind F1 is less severe as extra inductive line impedance increases the apparent impedance:Reach Setting: 0.8 x (10 – 3 – 5) = 1.6 Ω if the line-side (B) VTs are usedReach Setting: 0.8 x (10 – 4 – 3 – 5) = –1.6 Ω if the bus-side (A) VTs are usedThe negative value means that an underreaching zone cannot be used as the circuit between the potential source of therelay and an external fault for which the relay must not pick-up, is overcompensated, for example capacitive.At the Receiving Bus, consider a fault at F2:Reach Setting: 0.8 x (10 – 4 – 2) = 3.2 Ω if the line-side (B) VTs are usedReach Setting: 0.8 x (10 – 4 – 3 – 2) = 0.8 Ω if the bus-side (A) VTs are usedPractically, however, to cope with the effect of sub-synchronous oscillations, one can need to reduce the reach even more.As the characteristics of sub-synchronous oscillations are in complex relations with fault and system parameters, no solidsetting recommendations are given with respect to extra security margin for sub-synchronous oscillations. It is stronglyrecommended to use a power system simulator to verify the reach settings or to use an adaptive D60 feature for dynamicreach control.If the adaptive reach control feature is used, set the PHS DIST Z1 VOLT LEVEL setting accordingly.This setting is a sum of the overvoltage protection levels for all the series capacitors located between the relay potentialsource and the far-end busbar, or location for which the zone must not overreach. The setting is entered in pu of the phaseVT nominal voltage (RMS, not peak value).If a minimum fault current level (phase current) is causing a voltage drop across a given capacitor that prompts its air gapto flash over or its MOV to carry practically all the current, then the series capacitor is excluded from the calculations (thecapacitor is immediately by-passed by its overvoltage protection system and does not cause any overreach problems).
