GE L60 Instruction Manual

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9-10 L60 Line Phase Comparison System GE Multilin9.1 OVERVIEW 9 THEORY OF OPERATION9zero sequence network is generally quite different from that in the positive and negative sequence networks where the cur-rent distributions are approximately the same. For any given fault on a transmission line, the ratio of I_1F / I_2F at any ter-minal is the same as at any other terminal of that line. This is not true of either I_1F / I_0F or I_2F / I_0F. It is this thatmakes the use of zero sequence excitation undesirable.b) MIXED EXCITATIONIf the mixing network of Figure 9–5 were designed to produce an output that is proportional to I_2 – KI_1, this logic wouldthen be a simplified representation of a mixed excitation phase comparison scheme. In such schemes, the pick up settingof FDH must be high enough so that the KI_1 output from the mixing network does not result in continuous phase compari-son on load current (I_2 is normally zero during normal system conditions). Also, it may be desirable to have FDL set topick-up at some level above full load so that channel is not keyed on and off continuously during normal load conditions.Since FDH is set higher than FDL, this requirement results in a still higher setting for FDH.Because FDH controls tripping, this arrangement limits the applicability of the basic scheme to circuits where the minimumthree phase fault current is significantly higher than the maximum load current. The requirements for the satisfactory perfor-mance of a mixed excitation scheme using overcurrent fault detectors (FDH and FDL) are:• Both the FDL and FDH fault detectors must be set above full load current.• All internal faults regardless of type or the particular phases involved must produce enough I_2 - KI_1 to operate FDHat all ends of the line.• FDL must be set with a lower pick-up than FDH at the remote end(s) of the line for security during external faults.• The phase angle difference between the I_2 – KI_1 quantities obtained at all terminals of the protected line during alltypes of internal faults, and for any combination of phases, must be less than 115°.c) ZERO-SEQUENCE EXCITATIONWith zero sequence excitation the phase comparison portion of the overall scheme would not be capable of operating forphase-to-phase and three-phase faults. For this reason the overall protective scheme must include measurement functionsthat can detect and operate for faults involving any two or more phases. Mho type phase distance functions have typicallybeen employed for this protection.It should be noted that distance relays designed to operate for faults involving two or more phases will operate for double-phase-to-ground faults and also for certain close-in single-phase-to-ground faults. Thus, it is reasonable to expect that boththe phase comparison and distance protection will be activated for many faults.d) NEGATIVE-SEQUENCE EXCITATIONSince negative-sequence phase comparison protects against all unbalanced faults, the directional comparison functionsare required only for three-phase fault protection. However, if these functions are designed to respond to all multi phasefaults, then phase-to-phase and double phase-to-ground faults will be protected by both modes while single-phase-to-ground faults will be protected by only the phase comparison mode and three phase faults only by directional comparison.9.1.5 BLOCKING VS. TRIPPING SCHEMESa) INTRODUCTIONEarlier discussion in conjunction with Figure 9–2 provides a basis for further consideration of blocking vs. tripping pilotschemes. Figure 9–2C illustrates the comparer integrator logic for a tripping scheme using an ON-OFF type of pilot chan-nel. In order to trip, a receiver output is required to be present during the half cycle that the local current is positive. Figure9–2D is representative of a blocking pilot scheme where tripping will take place if there is no receiver output during the halfcycle that the local current is positive.If we consider that an input to, or an output from, a logic box is a positive going signal, the logic illustrated in Figures 9–2Aand 9–2C assume that a received signal at the input of a receiver will produce a positive going voltage signal at the outputof the receiver to the relay logic. This is not always true. Some types of receivers will produce negative (or reference) volt-age outputs when a signal is present at the input, and a positive signal output when nothing is received. If this were the sit-uation in Figure 9–2, Figure 9–2B would then represent a blocking scheme. In some applications where receiver outputsare inverted, the interface between the receiver and the relay logic includes an inverter (INV) which in effect inverts thereceiver output signal so that a received signal produces a positive going signal at the output of the inverter. The same gen-eral statements regarding signal polarities applies to the keying requirements for transmitters. Some transmitters mayrequire a positive signal while others a reference or negative signal to key them off of their quiescent states.