Keysight EXG and MXG X-Series Signal Generators User’s Guide 427Using the N5102A Digital Signal Interface Module for N5172B/82B with Option 003/004 and653/655/656/657Clock TimingClock Timing for Parallel Interleaved DataThe N5102A module provides the capability to interleave the digital I and Q samples. There are twochoices for interleaving:— IQ, where the I sample is transmitted first— QI, where the Q sample is transmitted firstWhen parallel interleaved is selected, all samples are transmitted on the I data lines. This effectivelytransmits the same number of samples during a sample period on half the number of data lines ascompared to non-interleaved samples. (A sample period consists of an I and Q sample.) Clocks persample is still a valid parameter for parallel interleaved transmissions and creates a reduction in thesample rate relative to the clock rate. The clocks per sample selection is the ratio of the reduction.Figure 17-5 shows each of the clocks per sample selections, for a parallel IQ interleaved portconfiguration, using a word sized of four bits and the clock timing relative to the I and Q samples.For a parallel QI interleaved port configuration, just reverse the I and Q sample positions. For inputmode, the clocks per sample setting is always one.Figure 17-5 Clock Timing for a Parallel IQ Interleaved Port ConfigurationQ sample4 bits per wordI sample4 bits per word1 Sample Period1 Clock Per Sample1 ClockThe I sample is transmitted on one clock transition and the Q sample is transmitted on theClockother transition; the sample and clock rates are the same.
