CHAPTER 10 WATCHDOG TIMERUser’s Manual U16227EJ2V0UD21410.4 Operation of Watchdog Timer10.4.1 Watchdog timer operation when “Ring-OSC cannot be stopped” is selected by mask optionThe operation clock of watchdog timer is fixed to the Ring-OSC.After reset is released, operation is started at the maximum cycle (bits 2, 1, and 0 (WDCS2, WDCS1, WDCS0) ofthe watchdog timer mode register (WDTM) = 1, 1, 1). The watchdog timer operation cannot be stopped.The following shows the watchdog timer operation after reset release.1. The status after reset release is as follows.• Operation clock: Ring-OSC clock• Cycle: fR/218 (1.09 seconds: At operation with fR = 240 kHz (TYP.))• Counting starts2. The following should be set in the watchdog timer mode register (WDTM) by an 8-bit memory manipulationinstructionNotes 1, 2.• Cycle: Set using bits 2 to 0 (WDCS2 to WDCS0)3. After the above procedures are executed, writing ACH to WDTE clears the count to 0, enabling recounting.Notes 1. The operation clock (Ring-OSC clock) cannot be changed. If any value is written to bits 3 and 4(WDCS3, WDCS4) of WDTM, it is ignored.2. As soon as WDTM is written, the counter of the watchdog timer is cleared.Caution In this mode, operation of the watchdog timer absolutely cannot be stopped even during STOPinstruction execution. For 8-bit timer H1 (TMH1), a division of the Ring-OSC can be selected asthe count source, so clear the watchdog timer using the interrupt request of TMH1 before thewatchdog timer overflows after STOP instruction execution. If this processing is not performed,an internal reset signal is generated when the watchdog timer overflows after STOP instructionexecution.
