NEC 78K0 User Manual

Also see for 78K/0 Series: User manual User manual User manual User manual User manual

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NEC 78K0 User Manual Manual pdf 361 page image

CHAPTER 20 POWER-ON-CLEAR CIRCUITUser’s Manual U16227EJ2V0UD 36120.4 Cautions for Power-on-Clear CircuitIn a system where the supply voltage (V DD ) fluctuates for a certain period in the vicinity of the POC detectionvoltage (V POC), the system may be repeatedly reset and released from the reset status. In this case, the time fromrelease of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.After releasing the reset signal, wait for the supply voltage fluctuation period of each system by means of asoftware counter that uses a timer, and then initialize the ports.Figure 20-3. Example of Software Processing After Release of Reset (1/2)• If supply voltage fluctuation is 50 ms or less in vicinity of POC detection voltageYesPower-on-clear; The Ring-OSC clock is set as the CPU clock when the reset signal is generated; The cause of reset (power-on-clear, WDT, LVI, or clock monitor)can be identified by the RESF register.; Change the CPU clock from the Ring-OSC clock to the X1 input clock.; Check the stabilization of oscillation of the X1 input clock by using theOSTC register.; TMIFH1 = 1: Interrupt request is generated.; Initialization of ports; 8-bit timer H1 can operate with the Ring-OSC clock.Source: f R (480 kHz (MAX.))/27 × compare value 200 = 53 ms(f R : Ring-OSC clock oscillation frequency)NoNote 1ResetChecking causeof resetNote 2Check stabilizationof oscillationChange CPU clock50 ms has passed?(TMIFH1 = 1?)InitializationprocessingStart timer(set to 50 ms)Notes 1. If reset is generated again during this period, initialization processing is not started.2. A flowchart is shown on the next page.