CHAPTER 3 CPU ARCHITECTUREUser’s Manual U16227EJ2V0UD 653.3.3 Table indirect addressing[Function]Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of theimmediate data of an operation code are transferred to the program counter (PC) and branched.This function is carried out when the CALLT [addr5] instruction is executed.This instruction references the address stored in the memory table from 40H to 7FH, and allows branching tothe entire memory space.[Illustration]15 115 0PC7 0Low Addr.High Addr.Memory (Table)Effective address+1Effective address 0 10 0 0 0 0 0 0 08 78 76 5 0011 17 6 5 1 0ta4–0Operation code3.3.4 Register addressing[Function]Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC)and branched.This function is carried out when the BR AX instruction is executed.[Illustration]7 0rp0 7A X15 0PC8 7