CHAPTER 15 INTERRUPT FUNCTIONSUser’s Manual U16227EJ2V0UD 32915.4.4 Interrupt request holdThere are instructions where, even if an interrupt request is issued for them while another instruction is beingexecuted, request acknowledgment is held pending until the end of execution of the next instruction. Theseinstructions (interrupt request hold instructions) are listed below.• MOV PSW, #byte• MOV A, PSW• MOV PSW, A• MOV1 PSW. bit, CY• MOV1 CY, PSW. bit• AND1 CY, PSW. bit• OR1 CY, PSW. bit• XOR1 CY, PSW. bit• SET1 PSW. bit• CLR1 PSW. bit• RETB• RETI• PUSH PSW• POP PSW• BT PSW. bit, $addr16• BF PSW. bit, $addr16• BTCLR PSW. bit, $addr16• EI• DI• Manipulation instructions for the IF0L, IF0H, IF1L, MK0L, MK0H, MK1L, PR0L, PR0H, and PR1L registersCaution The BRK instruction is not one of the above-listed interrupt request hold instructions. However,the software interrupt activated by executing the BRK instruction causes the IE flag to be clearedto 0. Therefore, even if a maskable interrupt request is generated during execution of the BRKinstruction, the interrupt request is not acknowledged.Figure 15-11 shows the timing at which interrupt requests are held pending.Figure 15-11. Interrupt Request HoldInstruction N Instruction M PSW and PC saved, jumpto interrupt servicingInterrupt servicingprogramCPU processing××IFRemarks 1. Instruction N: Interrupt request hold instruction2. Instruction M: Instruction other than interrupt request hold instruction3. The ××PR (priority level) values do not affect the operation of ××IF (interrupt request).
