1-12 Technical InformationFlash ROM programming is supported only in the 0F0000h – 0FFFFh area. The systemand Video BIOS area of the Flash ROM (upper 64 KB) can be erased, programmed, andverified normally with the RPG0 bit set low (to 0). To erase, program, and verify the SCSIBIOS and ACU area (lower 64 bits) the RPG0 bit must be set high (to 1). This allowsaccess to the lower 64 KB of the Flash ROM via the 0F000h to 0FFFFFh area.To upgrade the BIOS, see Section 4, Maintenance and Troubleshooting, for BIOS upgradeinformation.On-Board PeripheralsThe following subsections describe the computer’s on-board peripheral control circuitry.The peripherals interface with the computer through either the PCI or EISA buses.SCSI CircuitryThe SCSI circuitry is controlled by the Adaptec AIC-7850 PCI bus to SCSI bus controller.SCSI bus connectivity allows connection to SCSI-compatible peripherals, such as high-capacity floppy drives, tape drives, and CD-ROMs. The AIC-7850 can support datatransfer rates of up to 10 MBs per second. For further information, refer to the AdaptecAIC-7850 data manual.IDE ControllerThe CMD PCIO640B IDE controller supports up to four IDE hard disks. The PCIO640Bsupports both primary and secondary IDE devices. Automatic sensing of EISA hard diskcontrollers is provided. If the BIOS senses an EISA hard disk controller, the on-board IDEinterface is disabled. For further information, refer to the CMD PCIO640B data manual.Video CircuitryThe Tseng W32P PCI graphics accelerator features a graphical user interface (GUI)accelerator and advanced features for the developing imaging and multimedia markets. Forfurther information, refer to the Tseng W32P data manual.EISA SRAMA 6264LP 8Kx8 static RAM is used to configure the EISA bus. This SRAM receives itspower from the bq4287 real-time clock (RTC), which uses a lithium battery. The 6264LPis located on the EISA bus.
