RCA 301 Programmer's Reference Manual
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Q Logical "OR" (OR)s/sf^r bits.RepeatableGeneral DescriptionThis instruction is one of three instructions which provides the 301 system with bit manipulation abilities.It operates on equal length operands according to the rules outlined under "Outline of Operation below.FormatOperation — QN —Number (0-44) of characters in each operand. (See Appendix F-I.)A Address — HSM location of least significant digit of first operand and result.B Address — HSM location of least significant digit of second operand.Direction of OperationRight to left.Outline of OperationThis instruction operates in the following cycle:The contents of the N Register are examined. If zero, the instruction terminates. If other than zero, thecontents of the HSM location specified by the A Register are combined bit by bit with the contents of the HSMlocation specified by the B Register. This bit manipulation is combined according to the following rules:Bit in Bit in Bit in ResultFirst Operand Second Operand Bit in Result0 0 00 1 11 0 11 1 1The result of the combination is placed in the HSM location specified by the A Register. The contents of theA, B, and N Registers are decremented by one and the instruction is repeated.All six information bits of each operand enter the operation. The proper parity for each result character isgenerated as part of this instruction.Example of Rules(a) 1 00 1001 (b) 0 11 00011 01 0001 0 10 00110 01 1001 1 11 0011Final Register Contents(A)f = Address of location one to the left of the most significant digit of the result.(B)t — Ad dress of location one to the left of the most significant digit of second operand.TimingTotal time in microseconds= 21n + 35, where n is the number of characters in either operand (operands must be of equal lengths).VI-8 |
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