RCA 301 Programmer's Reference Manual
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W Conditional Transfer of Control (CTC)fGeneral DescriptionThis instruction senses the PRI's, the EF/ED, Overflow, and Interrupt Indicators, and the Simultaneous Mode.It can choose alternate sets of sequences of instructions.FormatOperation —WN — Indicates element to be sensed according to the following chart:N Indicator Sensed0 Nonex 1 PRI's2 Overflow Indicators4 Simultaneous Indicator8 EF/ED Normal Indicator& Interrupt Indicator— ( minus) EF/ED Simultaneous IndicatorPR'S FAt-L T>'T-iOA Address — Contains the address of the next instruction if one of the following sets of conditions is true:N = 1 and PRP set,N = 2 and the First Overflow Indicator is set,N = 4 and a "read" is in the Simultaneous Mode,N == 8 and the EF/ED Normal Indicator is set,N = & and the Interrupt Indicator is set (INT button on Console Panel is on), orN = — and the EF/ED Simultaneous Indicator is set.B Address — Contains the address of the next instruction if one of the following sets of conditions is true:N = 1 and PRN is set,N = 2 and neither Overflow Indicator is set, KfO over; :.WN = 4 and a "write" is in the Simultaneous Mode,N = 8 and the EF/ED Normal Indicator is not set,N = & and the Interrupt Indicator is not set, orN = — and the EE/ED Simultaneous Indicator is not set.Standard LocationSTP (on Transfer only)Outline of OperationThe N character is examined in the N Register. The condition is sensed and either the contents of the A or BRegister, as indicated above, are transferred to the P Register after the contents of the P Register are transferredto STP. The next instruction in sequence is performed if:1. N = 0, a register is not being sensed.2. N = 1, the PRI's are being sensed and PRZ is set.3. N = 2, the Second Overflow Indicator is being sensed and is set.4. N = 4, the Simultaneous Mode is being sensed and is found to be unoccupied.The first Overflow Indicator is set when a one is in the 24 bit position of the MSD of the sum. The SecondOverflow Indicator (present only in a 40,000 HSM) is set when a one is in the 25 bit position of the MSD of the sum.VII-5 |
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