Sanyo PLC-XF47 Service Manual

Also see for PLC-XF47: Brochure Specifications Owner's manual Owner's manual

Contents

- 138 -Electrical AdjustmentsPin No. Name Function Name Function Polarity I/O146 WAIT unused Hardware Wait I147 RESETM RESETM Manual Reset Demand I148 ADTRG / PTH[5] unused Analog Trigger / Input Port H I149 IOIS16 / PTG[7] unused IOIS16(PCMCIA) / Input Port G I150 ASEMD0 ASSEMD0[ICE] ASE Mode I151 PTG[5] / ASERKAK ASEBRKAK [ICE] ASE Break Acknowlege O152 PTG[4} unused Input Port G I153 PCC0BVD2 / PTG[3] / AUDATA[3] AUDATA[3] AUDATA[3] O154 PCC0BVD1 / PTG[2] / AUDATA[2] AUDATA[2] AUDATA[2] O155 Vss GND156 PCC0BCD2 / PTG[1] / AUDATA[1] AUDATA[1] AUDATA[1] O157 Vcc 1.9V158 PCC0BCD1 / PTG[0] / AUDATA[0] AUDATA[1] AUDATA[0] O159 VssQ GND160 PTF[7] / PINT[15] / TRST TRST Test Reset I161 VccQ 3.3V162 PTF[6] / PINT[14] / TRST TMS Test Mode Switch I163 PTF[5] / PINT[13] / TDI TDI Test Data Input I164 PTF[4] / PINT[12] / TCK TCK Test Clock I165 PTF[3] / PINT[11] unused Input Port F / Port Interrupt / Resarvation I / I / O166 PCCREG / PTF[2] / RESARVATION unused PCC REG / Input Port F / Resarvation O / I / O167 PCCVS1 / PTF[1] / RESARVATION unused PCC VS1 / Input Port F / Resarvation I / I / O168 PCCVS2 / PTF[0] / RESARVATION MOTHER_FPGA_NSTATUS Error Detect I169 MD0 MD0 Setting Clock Mode Always : L O / I / O170 Vcc_PLL1 1.9V Power PLL1171 CAP1 CAP1 PLL1 External Capacity Terminal172 Vss_PLL1 GND173 Vss_PLL2 GND174 CAP2 CAP2 PLL2 External Capacity Terminal175 Vcc_PLL2 1.9V Power PLL1176 PCC0WAIT / PTH[6] / AUDCK AUDCK AUD Clock I177 Vss GND178 Vcc 1.9V179 XTAL unused Clock Oscilator O180 EXTAL EXTAL External Clock / Crystal Oscilator [33.33333MHz] I181 LCD15 / PTM[3] / PINT[10] MOTHER_FPGA_DONE AUD Clock / Configuration Process End Signal I182 LCD14 / PTM[2] / PINT[9] SH_CHK_DPRAM PW_INT Clear Monitor (Input) "L" : Non Clear I183 LCD13 / PTM[1] / PINT[8] NIOS_FPGA_NSTATUS Error Detect I184 LCD12 / PTM[0] NIOS_FPGA_DONE Normary Ends Detect I185 STATUS0 / PTJ[6] READY_LED Ready LED Output "H" : ON O186 STATUS1 / PTJ[7] IC_RESET_CPU IC Power Conyrol O187 CL2 SH_FLASH_WP Flash Write Protect O188 VssQ GND189 CKIO CKIO System Clock Input / Output I / O190 VccQ 3.3V191 TxD0 / SCPT[0] SH_LB_UART Send Data (Network) 19200bps / 9600bps O192 SCK0 / SCPT[1] unused Serial Clock 0 / SCI IO Port IO / IO193 TxD_SIO / SCPT[2] unused SIOF Send Data / SCI Output Port O / O194 SIOMCLK / SCPT[3] unused SIOF Clock Input / SCI IO Port I / IO195 TxD2 / SCPT[4] SH_EX_UART Send Data ( External) 19200bps / 9600bps O196 SCK_SIO / SCPT[5] unused SIOFClock / SCI IO Port IO / IO197 SIOFSYNC / SCPT[6] unused SIOF Flame Sync / SCI Output Port IO / IO198 RxD0 / SCPT[0] LB_SH_UART Receive Data (Network) 19200bps / 9600bps I199 RxD_SIO / SCPT[2] unused SIOF Receive Data / SCI INput Port I / I200 Vss GND201 RxD2 / SCPT[4] EX_SH_UART Receive Data (external) 19200bps / 9600bps I202 Vcc 1.9V203 SCPT[7] / CTS2 / IRQ5 unused I / I / I204 LCD11 / PTC[7] / PINT[3] SH_SDA_Slot4 IIC Bus (Slot4) "L" : Active IO205 LCD10 / PTC[6] / PINT[2] SH_SCL_Slot4 IIC Bus (Slot4) "L" : Active IO206 LCD9 / PTC[5] / PINT[1] SH_SDA_Slot3 IIC Bus (Slot3) "L" : Active IO207 VssQ GND208 LCD8 / PTC[4] / PINT[0] SH_SCL_Slot3 IIC Bus (Slot3) "L" : Active IO209 VccQ 3.3V210 LCD7 / PTD[3] SH_SDA_3V IIC Bus "L" : Active IO211 LCD6 / PTD[2] SH_SCL_3V IIC Bus "L" : Active IO212 LCD5 / PTC[3] SH_SDA_Slot2 IIC Bus (Slot2) "L" : Active IO213 LCD4 / PTC[2] SH_SCL_Slot2 IIC Bus (Slot2) "L" : Active IO214 LCD3 / PTC[1] SH_SDA_Slot1 IIC Bus (Slot1) "L" : Active IO215 LCD2 / PTC[0] SH_SCL_Slot2 IIC Bus (Slot2) "L" : Active IO216 LCD1 / PTD[1] SH_SDA_S3V IIC Bus (Slot2) "L" : Active IO217 LCD0 / PTD[0] SH_SCL_Slot2 IIC Bus (Slot2) "L" : Active IO218 DREQ0 / PTD[4] PW_SH_0 PW --> SH Input signal I219 LCK / UCLK PTD[6] UCLK USB Clock (48MHz) I