Xilinx DS610 Datasheet

Contents

Spartan-3A DSP FPGA Family: DC and Switching CharacteristicsDS610 (v3.0) October 4, 2010 www.xilinx.comProduct Specification 23T IOICKPD Time from the active transition at theICLK input of the Input Flip-Flop (IFF) tothe point where data must be held at theInput pin. The Input Delay isprogrammed.LVCMOS25(3) 1 XC3SD1800A –1.40 –1.40 ns2 –2.11 –2.11 ns3 –2.48 –2.48 ns4 –2.77 –2.77 ns5 –2.62 –2.62 ns6 –3.06 –3.06 ns7 –3.42 –3.42 ns8 –3.65 –3.65 ns1 XC3SD3400A –1.31 –1.31 ns2 –1.88 –1.88 ns3 –2.44 –2.44 ns4 –2.89 –2.89 ns5 –2.83 –2.83 ns6 –3.33 –3.33 ns7 –3.63 –3.63 ns8 –3.96 –3.96 nsSet/Reset Pulse WidthT RPW_IOB Minimum pulse width to SR control inputon IOB– – All 1.33 1.61 nsNotes:1. The numbers in this table are tested using the methodology presented in Table 26 and are based on the operating conditions set forth inTable 7 and Table 10.2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add theappropriate Input adjustment from Table 22.3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtractthe appropriate Input adjustment from Table 22. When the hold time is negative, it is possible to change the data before the clock’s activeedge.Table 20: Sample Window (Source Synchronous)Symbol Description Max UnitsT SAMP Setup and holdcapture window ofan IOB flip-flop.The input capture sample window value is highly specific to a particular application, device,package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult theappropriate Xilinx Answer Record for application-specific values.• Answer Record 30879psTable 19: Setup and Hold Times for the IOB Input Path (Cont’d)Symbol Description Conditions DELAY_VALUE DeviceSpeedUnits-5 -4Min Min