Xilinx DS610 Datasheet

Contents

Spartan-3A DSP FPGA Family: DC and Switching CharacteristicsDS610 (v3.0) October 4, 2010 www.xilinx.comProduct Specification 50Suspend Mode TimingX-Ref Target - Figure 9Figure 9: Suspend Mode TimingTable 44: Suspend Mode Timing ParametersSymbol Description Min Typ Max UnitsEntering Suspend ModeT SUSPENDHIGH_AWAKE Rising edge of SUSPEND pin to falling edge of AWAKE pin without glitch filter(suspend_filter:No)– 7 – nsT SUSPENDFILTER Adjustment to SUSPEND pin rising edge parameters when glitch filterenabled (suspend_filter:Yes)+160 +300 +600 nsT SUSPEND_GTS Rising edge of SUSPEND pin until FPGA output pins drive their definedSUSPEND constraint behavior– 10 – nsT SUSPEND_GWE Rising edge of SUSPEND pin to write-protect lock on all writable clockedelements– <5 – nsT SUSPEND_DISABLE Rising edge of the SUSPEND pin to FPGA input pins and interconnectdisabled– 340 – nsExiting Suspend ModeT SUSPENDLOW_AWAKE Falling edge of the SUSPEND pin to rising edge of the AWAKE pin. Does notinclude DCM lock time.– 4 to 108 – μsT SUSPEND_ENABLE Falling edge of the SUSPEND pin to FPGA input pins and interconnectre-enabled– 3.7 to 109 – μsTAWAKE_GWE1 Rising edge of the AWAKE pin until write-protect lock released on all writableclocked elements, using sw_clk:InternalClock and sw_gwe_cycle:1.– 67 – nsTAWAKE_GWE512 Rising edge of the AWAKE pin until write-protect lock released on all writableclocked elements, using sw_clk:InternalClock and sw_gwe_cycle:512.– 14 – μsTAWAKE_GTS1 Rising edge of the AWAKE pin until outputs return to the behavior describedin the FPGA application, using sw_clk:InternalClock and sw_gts_cycle:1.– 57 – nsTAWAKE_GTS512 Rising edge of the AWAKE pin until outputs return to the behavior describedin the FPGA application, using sw_clk:InternalClock andsw_gts_cycle:512.– 14 – μsNotes:1. These parameters based on characterization.2. For information on using the Spartan-3A DSP Suspend feature, see XAPP480: Using Suspend Mode in Spartan-3 Generation FPGAs.DS610-3_08_061207BlockedtSUSPEND_DISABLEtSUSPEND_GWEtSUSPENDHIGH_AWAKEtAWAKE_GWEtAWAKE_GTStSUSPEND_GTSSUSPEND InputAWAKE OutputFlip-Flops, Block RAM,Distributed RAMFPGA OutputsFPGA Inputs,InterconnectWrite ProtectedDefined by SUSPEND constraintEntering Suspend Mode Exiting Suspend Modesw_gts_cyclesw_gwe_cycletSUSPEND_ENABLEtSUSPENDLOW_AWAKE