Xilinx DS610 Datasheet

Contents

Spartan-3A DSP FPGA Family: Introduction and Ordering InformationDS610 (v3.0) October 4, 2010 www.xilinx.comProduct Specification 3Architectural OverviewThe Spartan-3A DSP family architecture consists of five fundamental programmable functional elements:• XtremeDSP™ DSP48A Slice provides an 18-bit x18-bit multiplier, 18-bit pre-adder, 48-bitpost-adder/accumulator, and cascade capabilities forvarious DSP applications.• Block RAM provides data storage in the form of18-Kbit dual-port blocks.• Configurable Logic Blocks (CLBs) contain flexibleLook-Up Tables (LUTs) that implement logic plusstorage elements used as flip-flops or latches. CLBsperform a wide variety of logical functions as well asstore data.• Input/Output Blocks (IOBs) control the flow of databetween the I/O pins and the internal logic of thedevice. IOBs support bidirectional data flow plus3-state operation. Supports a variety of signalstandards, including several high-performancedifferential standards. Double Data-Rate (DDR)registers are included.• Digital Clock Manager (DCM) Blocks provideself-calibrating, fully digital solutions for distributing,delaying, multiplying, dividing, and phase-shifting clocksignals.These elements are organized as shown in Figure 1. A dualring of staggered IOBs surrounds a regular array of CLBs.The XC3SD1800A has four columns of DSP48As, and theXC3SD3400A has five columns of DSP48As. EachDSP48A has an associated block RAM. The DCMs arepositioned in the center with two at the top and two at thebottom of the device and in the two outer columns of the 4 or5 columns of block RAM and DSP48As.The Spartan-3A DSP family features a rich network ofrouting that interconnect all five functional elements,transmitting signals among them. Each functional elementhas an associated switch matrix that permits multipleconnections to the routing.X-Ref Target - Figure 1Figure 1: Spartan-3A DSP Family ArchitectureCLBBlock RAMDCMIOBsIOBsDS610-1_01_031207IOBsIOBsDCMBlock RAM / DSP48A SliceDCMCLBsIOBsDSP48A SliceNotes:1. The XC3SD1800A and XC3SD3400A have two DCMs on both the left and right sides, as well as the two DCMs at the top andbottom of the devices. The two DCMs on the left and right of the chips are in the middle of the outer Block RAM/DSP48Acolumns of the 4 or 5 columns in the selected device, as shown in the diagram above.2. A detailed diagram of the DSP48A can be found in UG431: XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide.