Xilinx DS610 Datasheet

Contents

Spartan-3A DSP FPGA Family: DC and Switching CharacteristicsDS610 (v3.0) October 4, 2010 www.xilinx.comProduct Specification 38Configurable Logic Block (CLB) TimingTable 29: CLB (SLICEM) TimingSymbol DescriptionSpeed GradeUnits-5 -4Min Max Min MaxClock-to-Output TimesT CKO When reading from the FFX (FFY) Flip-Flop, the timefrom the active transition at the CLK input to dataappearing at the XQ (YQ) output– 0.60 – 0.68 nsSetup TimesTAS Time from the setup of data at the F or G input to theactive transition at the CLK input of the CLB0.18 – 0.36 – nsT DICK Time from the setup of data at the BX or BY input tothe active transition at the CLK input of the CLB1.58 – 1.88 – nsHold TimesTAH Time from the active transition at the CLK input to thepoint where data is last held at the F or G input0.00 – 0.00 – nsT CKDI Time from the active transition at the CLK input to thepoint where data is last held at the BX or BY input0.00 – 0.00 – nsClock TimingT CH The High pulse width of the CLB’s CLK signal 0.63 – 0.75 – nsT CL The Low pulse width of the CLK signal 0.63 – 0.75 – nsF TOG Toggle frequency (for export control) 0 770 0 667 MHzPropagation TimesT ILO The time it takes for data to travel from the CLB’sF (G) input to the X (Y) output– 0.62 – 0.71 nsSet/Reset Pulse WidthT RPW_CLB The minimum allowable pulse width, High or Low, tothe CLB’s SR input1.33 – 1.61 – nsNotes:1. The numbers in this table are based on the operating conditions set forth in Table 7.