Xilinx DS610 Datasheet

Contents

Spartan-3A DSP FPGA Family: DC and Switching CharacteristicsDS610 (v3.0) October 4, 2010 www.xilinx.comProduct Specification 33The capacitive load (C L ) is connected between the output and GND. The Output timing for all standards, as published in thespeed files and the data sheet, is always based on a CL value of zero. High-impedance probes (less than 1 pF) are used forall measurements. Any delay that the test fixture might contribute to test measurements is subtracted from thosemeasurements to produce the final timing numbers as published in the speed files and data sheet.DifferentialLVDS_25 – VICM – 0.125 VICM + 0.125 50 1.2 VICMLVDS_33 – VICM – 0.125 VICM + 0.125 50 1.2 VICMBLVDS_25 – VICM – 0.125 VICM + 0.125 1M 0 VICMMINI_LVDS_25 – VICM – 0.125 VICM + 0.125 50 1.2 VICMMINI_LVDS_33 – VICM – 0.125 VICM + 0.125 50 1.2 VICMLVPECL_25 – VICM – 0.3 VICM + 0.3 N/A N/A VICMLVPECL_33 – VICM – 0.3 VICM + 0.3 N/A N/A VICMRSDS_25 – VICM – 0.1 VICM + 0.1 50 1.2 VICMRSDS_33 – VICM – 0.1 VICM + 0.1 50 1.2 VICMTMDS_33 – VICM – 0.1 VICM + 0.1 50 3.3 VICMPPDS_25 – VICM – 0.1 VICM + 0.1 50 0.8 VICMPPDS_33 – VICM – 0.1 VICM + 0.1 50 0.8 VICMDIFF_HSTL_I_18 – VICM – 0.5 VICM + 0.5 50 0.9 VICMDIFF_HSTL_II_18 – VICM – 0.5 VICM + 0.5 50 0.9 VICMDIFF_HSTL_III_18 – VICM – 0.5 VICM + 0.5 50 1.8 VICMDIFF_HSTL_I – VICM – 0.5 VICM + 0.5 50 0.9 VICMDIFF_HSTL_III – VICM – 0.5 VICM + 0.5 50 0.9 VICMDIFF_SSTL18_I – VICM – 0.5 VICM + 0.5 50 0.9 VICMDIFF_SSTL18_II – VICM – 0.5 VICM + 0.5 50 0.9 VICMDIFF_SSTL2_I – VICM – 0.5 VICM + 0.5 50 1.25 VICMDIFF_SSTL2_II – VICM – 0.5 VICM + 0.5 50 1.25 VICMDIFF_SSTL3_I – VICM – 0.5 VICM + 0.5 50 1.5 VICMDIFF_SSTL3_II – VICM – 0.5 VICM + 0.5 50 1.5 VICMNotes:1. Descriptions of the relevant symbols are:VREF – The reference voltage for setting the input switching thresholdVICM – The common mode input voltageVM – Voltage of measurement point on signal transitionVL – Low-level test voltage at Input pinVH – High-level test voltage at Input pinRT – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is requiredVT – Termination voltage2. The load capacitance (C L ) at the Output pin is 0 pF for all signal standards.3. According to the PCI specification. For information on PCI IP solutions, see www.xilinx.com/pci. The PCIX IOSTANDARD is available andhas equivalent characteristics but no PCI-X IP is supported.Table 26: Test Methods for Timing Measurement at I/Os (Cont’d)Signal Standard(IOSTANDARD)Inputs Outputs(2) Inputs andOutputsVREF (V) VL (V) VH (V) RT (Ω) VT (V) VM (V)