Xilinx DS610 Datasheet
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Spartan-3A DSP FPGA Family: Pinout DescriptionsDS610 (v3.0) October 4, 2010 www.xilinx.comProduct Specification 87XC3SD3400A FPGATable 68 lists all the FG676 package pins for the XC3SD3400A FPGA. They are sorted by bank number and then by pinname. Pairs of pins that form a differential I/O pair appear together in the table. Table 68 also shows the pin number for eachpin and the pin type, as defined earlier.An electronic version of this package pinout table and footprint diagram is available for download from the Xilinx website at:www.xilinx.com/support/documentation/data_sheets/s3a_pin.zip.Pinout TableNote: The grayed boxes denote a difference between the XC3SD1800A and the XC3SD3400A devices.Table 68: Spartan-3A DSP FG676 Pinout forXC3SD3400A FPGABank XC3SD3400A Pin Name FG676Ball Type0 IO_L43N_0 K11 I/O0 IO_L39N_0 K12 I/O0 IO_L25P_0/GCLK4 K14 GCLK0 IO_L12N_0 K16 I/O0 IP_0 J10 INPUT0 IO_L43P_0 J11 I/O0 IO_L39P_0 J12 I/O0 IP_0 J13 INPUT0 IO_L25N_0/GCLK5 J14 GCLK0 IP_0 J15 INPUT0 IO_L12P_0 J16 I/O0 IP_0/VREF_0 J17 VREF0 IO_L47N_0 H9 I/O0 IO_L46N_0 H10 I/O0 IO_L35N_0 H12 I/O0 IP_0 H13 INPUT0 IO_L16N_0 H15 I/O0 IO_L08P_0 H17 I/O0 IP_0 H18 INPUT0 IO_L52N_0/PUDC_B G8 DUAL0 IO_L47P_0 G9 I/O0 IO_L46P_0 G10 I/O0 IP_0/VREF_0 G11 VREF0 IO_L35P_0 G12 I/O0 IO_L27N_0/GCLK9 G13 GCLK0 IP_0 G14 INPUT0 IO_L16P_0 G15 I/O0 IO_L08N_0 G17 I/O0 IO_L02P_0/VREF_0 G19 VREF0 IO_L01P_0 G20 I/O0 IO_L48P_0 F7 I/O0 IO_L52P_0/VREF_0 F8 VREF0 IO_L31N_0 F12 I/O0 IO_L27P_0/GCLK8 F13 GCLK0 IO_L24N_0 F14 I/O0 IO_L20P_0 F15 I/O0 IO_L13P_0 F17 I/O0 IO_L02N_0 F19 I/O0 IO_L01N_0 F20 I/O0 IO_L48N_0 E7 I/O0 IO_L37P_0 E10 I/O0 IP_0 E11 INPUT0 IO_L31P_0 E12 I/O0 IO_L24P_0 E14 I/O0 IO_L20N_0/VREF_0 E15 VREF0 IO_L13N_0 E17 I/O0 IP_0 E18 INPUT0 IO_L10P_0 E21 I/O0 IO_L44N_0 D6 I/O0 IP_0/VREF_0 D7 VREF0 IO_L40N_0 D8 I/O0 IO_L37N_0 D9 I/O0 IO_L34N_0 D10 I/O0 IO_L32N_0/VREF_0 D11 VREF0 IP_0 D12 INPUT0 IO_L30P_0 D13 I/O0 IP_0/VREF_0 D14 VREF0 IO_L22P_0 D16 I/O0 IO_L21P_0 D17 I/O0 IO_L17P_0 D18 I/O0 IO_L11P_0 D20 I/OTable 68: Spartan-3A DSP FG676 Pinout forXC3SD3400A FPGA (Cont’d)Bank XC3SD3400A Pin Name FG676Ball Type |
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