Xilinx RocketIO User Manual

Also see for RocketIO: User guide User guide User guide

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Xilinx RocketIO User Manual Manual pdf 108 page image

108 www.xilinx.com RocketIO™ Transceiver User GuideUG024 (v3.0) February 22, 2007Chapter 3: Analog Design ConsiderationsRDeterministic Jitter (DJ) is data pattern dependant jitter, attributed to a unique source (e.g.,Inter Symbol Interference (ISI) due to loss effects of the media). DJ is linearly additive.Random Jitter (RJ) is due to stochastic sources, such as substrate, power supply, etc. RJ isadditive as the sum of squares, and follows a bell curve.Clock and Data RecoveryThe serial transceiver input is locked to the input data stream through Clock and DataRecovery (CDR), a built-in feature of the RocketIO transceiver. CDR keys off the rising andfalling edges of incoming data and derives a clock that is representative of the incomingdata rate.The derived clock, RXRECCLK, is presented to the FPGA fabric at 1/20th the incomingdata rate (whether full-rate or half-rate). This clock is generated and remains locked aslong as it remains within the specified component range. This range is shown in Table 3-4.A sufficient number of transitions must be present in the data stream for CDR to workproperly. The CDR circuit is guaranteed to work with 8B/10B encoding. Further, CDRrequires approximately 5,000 transitions upon power-up to guarantee locking to theincoming data rate. Once lock is achieved, up to 75 missing transitions can be toleratedbefore lock to the incoming data stream is lost.Table 3-4: CDR ParametersParameter Min Typ Max Units ConditionsFrequency Range Serial input, diff.(RXP/RXN)300 1,562.5 MHzTDCREF REFCLK(1) duty cycle 45 50 55 %TRCLK/TFCLK REFCLK (1) rise andfall time (seeVirtex-II Pro DataSheet, Module 3)600 1000 ps Between 20%and 80% voltagelevelsTGJTT REFCLK(1) totaljitter, (2) peak-to-peak40 ps 3.125 Gb/s50 ps 2.5 Gb/s120 ps 1.06 Gb/sTLOCK (3) Clock recoveryfrequency acquisitiontime10 μs From systemreset. Much lesstime is needed tolock if loss ofsync occurs(T phase ), which isdescribed in DataSheet Module 3.TUNLOCK cyclesPLL length 75 non-transitionsRequirementwhen bypassing8B/10BNotes:1. BREFCLK for speeds of 2.5 Gb/s or greater.2. Jitter measured at BGA ball.3. T LOCK depends on serial speed and length/type of sequence used.Product Not Recommended for New Designs