Xilinx RocketIO User Manual

Also see for RocketIO: User guide User guide User guide

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Xilinx RocketIO User Manual Manual pdf 109 page image

RocketIO™ Transceiver User Guide www.xilinx.com 109UG024 (v3.0) February 22, 2007PCB Design Requirements RAn additional feature of CDR is its ability to accept an external precision clock, REFCLK,which either acts to clock incoming data or to assist in synchronizing the derivedRXRECCLK.For further clarity, TXUSRCLK is used to clock data from the FPGA core to the TX FIFO.The FIFO depth accounts for the slight phase difference between these two clocks. If theclocks are locked in frequency, then the FIFO acts much like a pass-through buffer.PCB Design RequirementsTo ensure reliable operation of the RocketIO transceivers, certain requirements must bemet by the designer. This section outlines these requirements governing power filteringnetworks, high-speed differential signal traces, and reference clocks. Any designs that donot adhere to these requirements will not be supported by Xilinx, Inc.Power ConditioningEach RocketIO transceiver has five power supply pins, all of which are sensitive to noise.Table 3-5 summarizes the power supply pins, their names, and associated voltages. Forpower and current requirements of each supply, refer to the data sheet (DS083).To operate properly, the RocketIO transceiver requires a certain level of noise isolationfrom surrounding noise sources. For this reason, it is required that both dedicated voltageregulators and passive high-frequency filtering be used to power the RocketIO circuitry.Voltage Regulator Selection and UseXilinx has qualified a number of linear regulators for use with RocketIO transceivers.RocketIO supplies must be powered by voltage regulators meeting the following criteria:• Must be a linear or LDO regulator (switching or DC/DC converter is not acceptable).• Must be used in the circuit given in Figure 3-7.• Must either be a qualified linear regulator listed in Table 3-6 or meet the followingcriteria:Table 3-5: Transceiver Power Supply RangesSupply 2.5V±5%1.8V -2.625V1.6V -1.8V DescriptionAVCCAUXRX √ Analog RX supplyAVCCAUXTX √ Analog TX supplyVTRX (1) √ √ RX termination supplyVTTX(2) √ TX termination supplyGNDA Analog ground for transmit andreceive analog suppliesNotes:1. See section “AC and DC Coupling,” page 117, and Table 3-8 for VTRX supply restrictions in AC- andDC-coupled cases.2. Pre-emphasis and swing settings are optimal at VTTX = 2.5V ±5%. VTTX can be powered with as lowas 1.8V in applications with data rates below 1.25 Gb/s (LVDS interfacing). Contact your Xilinx FAEfor more information on such interfaces.Product Not Recommended for New Designs