42 www.xilinx.com RocketIO™ Transceiver User GuideUG024 (v3.0) February 22, 2007Chapter 2: Digital Design ConsiderationsRClock RatioUSRCLK2 clocks the data buffers. The ability to send/receive parallel data to/from thetransceiver at three different widths requires the user to change the frequency ofUSRCLK2. This creates a frequency ratio between USRCLK and USRCLK2. The fallingedges of the clocks must align. Table 2-4 shows the ratios for each of the three data widths.Digital Clock Manager (DCM) ExamplesWith at least three different clocking schemes possible on the transceiver, a DCM is the bestway to create these schemes.Table 2-5 shows typical DCM connections for several transceiver clocks. REFCLK is theinput reference clock for the DCM. The other clocks are generated by the DCM. The DCMestablishes a desired phase relationship between TXUSRCLK, TXUSRCLK2, etc. in theFPGA core and REFCLK at the pad.NOTE: The reference clock may be any of the four MGT clocks, including the BREFCLKs.FF672 B14/C14 C13/B13 AD14/AE14 AE13/AD13FF896 F16/G16 G15/F15 AH16/AJ16 AJ15/AH15FF1152 H18/J18 J17/H17 AK18/AL18 AL17/AK17FF1148 N/A N/A N/A N/AFF1517 E20/D20 J20/K20 AR20/AT20 AL20/AK20FF1704 G22/F22 F21/G21 AU22/AT22 AT21/AU21FF1696 N/A N/A N/A N/ATable 2-3: BREFCLK Pin NumbersPackageTop BottomBREFCLKPin NumberBREFCLK2Pin NumberBREFCLKPin NumberBREFCLK2Pin NumberTable 2-4: Data Width Clock RatiosData Width Frequency Ratio of USRCLK\USRCLK21 byte 1:2 (1)2 byte 1:14 byte 2:1 (1)Notes:1. Each edge of the slower clock must align with the falling edge of the faster clock.Product Not Recommended for New Designs
